Spartan-3E FPGA Family: Functional Description
W
Table 54 shows the connections between the SPI Flash
controls are not used by the FPGA during configuration.
However, the HOLD pin must be High during the
configuration process. The PROM’s write protect input must
be High in order to write or program the Flash memory.
PROM and the FPGA’s SPI configuration interface. Each
SPI Flash PROM vendor uses slightly different signal
naming. The SPI Flash PROM’s write protect and hold
Table 54: Example SPI Flash PROM Connections and Pin Naming
Silicon
Storage
Technology
Atmel
DataFlash
SPI Flash Pin
FPGA Connection
STMicro
NexFlash
DATA_IN
DATA_OUT
SELECT
CLOCK
MOSI
DIN
D
Q
S
C
DI
DO
CS
SI
SI
SO
SO
CSO_B
CCLK
CE#
SCK
CS
CLK
SCK
Not required for FPGA configuration. Must be High
to program SPI Flash. Optional connection to
FPGA user I/O after configuration.
WR_PROTECT
W
WP
WP#
WP
N/A
W
Not required for FPGA configuration but must be
High during configuration. Optional connection to
FPGA user I/O after configuration. Not applicable
to Atmel DataFlash.
HOLD
(see Figure 53)
HOLD
HOLD
HOLD#
Only applicable to Atmel DataFlash. Not required
for FPGA configuration but must be High during
configuration. Optional connection to FPGA user
I/O after configuration. Do not connect to FPGA’s
PROG_B as this will prevent direct programming of
the DataFlash.
RESET
(see Figure 54)
N/A
N/A
N/A
N/A
N/A
N/A
RESET
Only applicable to Atmel DataFlash and only
available on certain packages. Not required for
FPGA configuration. Output from DataFlash
PROM. Optional connection to FPGA user I/O after
configuration.
RDY/BUSY
(see Figure 54)
RDY/BUSY
The mode select pins, M[2:0], and the variant select pins,
VS[2:0] are sampled when the FPGA’s INIT_B output goes
High and must be at defined logic levels during this time.
After configuration, when the FPGA’s DONE output goes
High, these pins are all available as full-featured user-I/O
pins.
disable the pull-up resistors. The HSWAP control must
remain at a constant logic level throughout FPGA
configuration. After configuration, when the FPGA’s DONE
output goes High, the HSWAP pin is available as
full-featured user-I/O pin and is powered by the VCCO_0
supply.
In a single-FPGA application, the FPGA’s DOUT pin is not
used but is actively driving during the configuration process.
P
Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins or High to
Table 55: Serial Peripheral Interface (SPI) Connections
FPGA
Pin Name
Description
During Configuration
After Configuration
User I/O
Direction
HSWAP
Input
User I/O Pull-Up Control. When Low
during configuration, enables pull-up
resistors in all I/O pins to respective I/O
bank VCCO input.
Drive at valid logic level
throughout configuration.
P
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode. See Design
Considerations for the HSWAP, M[2:0],
and VS[2:0] Pins.
M2 = 0, M1 = 0, M0 = 1.
Sampled when INIT_B goes
High.
User I/O
DS312 (v4.2) December 14, 2018
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Product Specification
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