Spartan-3E FPGA Family: Functional Description
Figure 57, page 83 demonstrates how to configure multiple
FPGAs with different configurations, all stored in a single
SPI Flash. The diagram uses standard SPI Flash memories
but the same general technique applies for Atmel
DataFlash.
X-Ref Target - Figure 54
+1.2V
+3.3V
Atmel
AT45DB
VCCINT
DataFlash
P
P
HSWAP
VCCO_0
VCCO_0
I
VCC
VCCO_2
MOSI
+3.3V
SI
Power-on monitor is only required if
+3.3V (VCCO_2) supply is the last supply
SPI Mode
DIN
SO
in power-on sequence, after VCCINT
and VCCAUX. Must delay FPGA
configuration for > 20 ms after SPI
DataFlash reaches its minimum VCC.
Force FPGA INIT_B input OR PROG_B
input Low with an open-drain or open-
collector driver.
‘0’
‘0’
‘1’
M2
M1
M0
CSO_B
CS
W
WP
‘1’
RESET
RDY/BUSY
SCK
Spartan-3E
Variant Select
FPGA
‘1’
‘1’
‘0’
VS2
VS1
VS0
GND
+3.3V
+3.3V
CCLK
DOUT
INIT_B
Power-On
Monitor
INIT_B
+2.5V
JTAG
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TMS
TCK
TDO
TMS
TCK
or
PROG_B
DONE
+3.3V
GND
Power-On
Monitor
PROG_B
PROG_B
Recommend
open-drain
driver
DS312-2_50a_082009
Figure 54: Atmel SPI-based DataFlash Configuration Interface
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
76
XILINX [ XILINX, INC ]
