Spartan-3E FPGA Family: Functional Description
multiple (for multiplication) of the incoming clock frequency.
The CLK2X output produces an in-phase signal that is twice
the frequency of CLKIN. The CLK2X180 output also
doubles the frequency, but is 180° out-of-phase with respect
to CLKIN. The CLKDIV output generates a clock frequency
that is a predetermined fraction of the CLKIN frequency.
The CLKDV_DIVIDE attribute determines the factor used to
divide the CLKIN frequency. The attribute can be set to
various values as described in Table 29. The basic
Accommodating Input Frequencies Beyond Spec-
ified Maximums
If the CLKIN input frequency exceeds the maximum
permitted, divide it down to an acceptable value using the
CLKIN_DIVIDE_BY_2 attribute. When this attribute is set to
“TRUE”, the CLKIN frequency is divided by a factor of two
as it enters the DCM. In addition, the CLKIN_DIVIDE_BY_2
option produces a 50% duty-cycle on the input clock,
although at half the CLKIN frequency.
frequency synthesis outputs are described in Table 28.
Quadrant and Half-Period Phase Shift Outputs
Duty Cycle Correction of DLL Clock Outputs
In addition to CLK0 for zero-phase alignment to the CLKIN
signal, the DLL also provides the CLK90, CLK180, and
CLK270 outputs for 90°, 180°, and 270° phase-shifted
signals, respectively. These signals are described in
Table 28, page 48 and their relative timing is shown in
Figure 43. For control in finer increments than 90°, see
Phase Shifter (PS).
The DLL output signals exhibit a 50% duty cycle, even if the
incoming CLKIN signal has a different duty cycle.
Fifty-percent duty cycle means that the High and Low times
of each clock cycle are equal.
DLL Performance Differences Between Steppings
As indicated in Digital Clock Manager (DCM) Timing
(Module 3), the Stepping 1 revision silicon supports higher
maximum input and output frequencies. Stepping 1 devices
are backwards compatible with Stepping 0 devices.
X-Ref Target - Figure 43
0o 90o 180o 270o 0o 90o 180o 270o 0o
Phase:
Input Signal (40%/60% Duty Cycle)
Digital Frequency Synthesizer (DFS)
t
The DFS unit generates clock signals where the output
frequency is a product of the CLKIN input clock frequency
and a ratio of two user-specified integers. The two
dedicated outputs from the DFS unit, CLKFX and
CLKFX180, are defined in Table 33.
CLKIN
Output Signal - Duty Cycle Corrected
Table 33: DFS Signals
CLK0
Signal
CLKFX
Direction
Description
CLK90
CLK180
CLK270
Output
Multiplies the CLKIN frequency by
the attribute-value ratio
(CLKFX_MULTIPLY/
CLKFX_DIVIDE) to generate a
clock signal with a new target
frequency.
CLKFX180
Output
Generates a clock signal with the
same frequency as CLKFX, but
shifted 180° out-of-phase.
CLK2X
CLK2X180
CLKDV
The signal at the CLKFX180 output is essentially an
inversion of the CLKFX signal. These two outputs always
exhibit a 50% duty cycle, even when the CLKIN signal does
not. The DFS clock outputs are active coincident with the
seven DLL outputs and their output phase is controlled by
the Phase Shifter unit (PS).
DS099-2_10_101105
Figure 43: Characteristics of the DLL Clock Outputs
The output frequency (f
) of the DFS is a function of the
CLKFX
Basic Frequency Synthesis Outputs
incoming clock frequency (f
attributes, as follows.
) and two integer
CLKIN
The DLL component provides basic options for frequency
multiplication and division in addition to the more flexible
synthesis capability of the DFS component, described in a
later section. These operations result in output clock signals
with frequencies that are either a fraction (for division) or a
CLKFX_MULTIPLY
f
= f
• ---------------------------------------------------
Eq 1
CLKFX
CLKIN
CLKFX_DIVIDE
The CLKFX_MULTIPLY attribute is an integer ranging from
2 to 32, inclusive, and forms the numerator in Equation 1.
DS312 (v4.2) December 14, 2018
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Product Specification
53
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