Spartan-3E FPGA Family: Functional Description
DLL Attributes and Related Functions
cancel out the clock skew. When the DLL phase-aligns the
CLK0 signal with the CLKIN signal, it asserts the LOCKED
output, indicating a lock on to the CLKIN signal.
The DLL unit has a variety of associated attributes as
described in Table 29. Each attribute is described in detail in
the sections that follow.
Table 29: DLL Attributes
Attribute
Description
Values
CLK_FEEDBACK
CLKIN_DIVIDE_BY_2
CLKDV_DIVIDE
Chooses either the CLK0 or CLK2X output to drive NONE, 1X, 2X
the CLKFB input
Halves the frequency of the CLKIN signal just as it FALSE, TRUE
enters the DCM
Selects the constant used to divide the CLKIN input 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0, 6.5, 7.0,
frequency to generate the CLKDV output frequency 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16
CLKIN_PERIOD
Additional information that allows the DLL to
operate with the most efficient lock time and the
best jitter tolerance
Floating-point value representing the
CLKIN period in nanoseconds
DLL Clock Input Connections
For best results, an external clock source enters the FPGA
via a Global Clock Input (GCLK). Each specific DCM has
four possible direct, optimal GCLK inputs that feed the
DCM’s CLKIN input, as shown in Table 30. Table 30 also
provides the specific pin numbers by package for each
GCLK input. The two additional DCM’s on the XC3S1200E
and XC3S1600E have similar optimal connections from the
left-edge LHCLK and the right-edge RHCLK inputs, as
described in Table 31 and Table 32.
Design Note
Avoid using global clock input GCLK1 as it is always shared
with the M2 mode select pin. Global clock inputs GCLK0,
GCLK2, GCLK3, GCLK12, GCLK13, GCLK14, and
GCLK15 have shared functionality in some configuration
modes.
•
The DCM supports differential clock inputs (for
example, LVDS, LVPECL_25) via a pair of GCLK inputs
that feed an internal single-ended signal to the DCM’s
CLKIN input.
DS312 (v4.2) December 14, 2018
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Product Specification
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