Spartan-3E FPGA Family: Functional Description
Table 31: Direct Clock Input and Optional External Feedback to Left-Edge DCMs (XC3S1200E and XC3S1600E)
Single-Ended Pin Number by Package Type
Left Edge
Diff.
Clock
VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484
LHCLK
DCM/BUFGMUX
BUFGMUX_X0Y5
BUFGMUX_X0Y4
D
C
P
N
P
N
P9
F3
F2
F1
G1
P14
P15
P16
P17
P22
P23
P24
P25
H5
H6
H3
H4
J5
J4
J1
J2
K3
K2
K7
L7
M5
L5
LHCLK0
LHCLK1
LHCLK2
LHCLK3
P10
P11
P12
DCM_X0Y2
L8
M8
BUFGMUX_X0Y3
BUFGMUX_X0Y2
B
A
BUFGMUX_X0Y9
BUFGMUX_X0Y8
H
G
P
N
P
N
P15
P16
P17
P18
G3
H1
H2
H3
P20
P21
P22
P23
P28
P29
P30
P31
J2
J3
J5
J4
K3
K4
K6
K5
M1
L1
M1
N1
M3
M4
LHCLK4
LHCLK5
LHCLK6
LHCLK7
DCM_X0Y1
M3
L3
BUFGMUX_X0Y7
BUFGMUX_X0Y6
F
E
Table 32: Direct Clock Input and Optional External Feedback to Right-Edge DCMs (XC3S1200E and XC3S1600E)
Right Edge
DCM/BUFGMUX
Single-Ended Pin Number by Package Type
Diff.
Clock
RHCLK
VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484
D
C
BUFGMUX_X3Y5
BUFGMUX_X3Y4
RHCLK7
RHCLK6
RHCLK5
RHCLK4
P68
P67
P66
P65
G13
G14
H12
H13
P94
P93
P92
P91
P135
P134
P133
P132
H11
H12
H14
H15
J14
J15
J16
J17
J20
K20
K14
K13
L19
L18
L21
L20
N
P
N
P
DCM_X3Y2
B
A
BUFGMUX_X3Y3
BUFGMUX_X3Y2
H
G
BUFGMUX_X3Y9
BUFGMUX_X3Y8
RHCLK3
RHCLK2
RHCLK1
RHCLK0
P63
P62
P61
P60
J14
J13
J12
K14
P88
P87
P86
P85
P129
P128
P127
P126
J13
J14
J16
K16
K14
K15
K12
K13
L14
L15
L16
M16
M16
M15
M22
N22
N
P
N
P
DCM_X3Y1
F
E
BUFGMUX_X3Y7
BUFGMUX_X3Y6
Every FPGA input provides a possible DCM clock input, but
the path is not temperature and voltage compensated like
the GCLKs. Alternatively, clock signals within the FPGA
optionally provide a DCM clock input via a Global Clock
Multiplexer Buffer (BUFGMUX). The global clock net
connects directly to the CLKIN input. The internal and
external connections are shown in Figure 42a and
Figure 42c, respectively.
DS312 (v4.2) December 14, 2018
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Product Specification
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