Spartan-3E FPGA Family: Functional Description
Table 30: Direct Clock Input Connections and Optional External Feedback to Associated DCMs
Differential Pair Differential Pair Differential Pair
Differential Pair
Package
N
P
N
P
N
P
N
P
Pin Number for Single-Ended Input
Pin Number for Single-Ended Input
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
P91
B7
P90
A7
P89
C8
P88
B8
P86
A9
P85
B9
P84
C9
P83
A10
P131
P186
D8
P130
P185
C8
P129
P184
B8
P128
P183
A8
P126
P181
A9
P125
P180
A10
P123
P178
F9
P122
P177
E9
D9
C9
B9
B8
A10
E10
C12
B10
E10
G11
E12
D10
F11
A9
A10
C11
G10
H11
H10
H12
E11
B11
B12
F12
Associated Global Buffers
GCLK11 GCLK10 GCLK9
GCLK8
GCLK7
GCLK6
GCLK5
GCLK4
Top Left DCM
Top Right DCM
XC3S100: N/A
XC3S100: DCM_X0Y1
XC3S250E, XC3S500E: DCM_X0Y1
XC3S1200E, XC3S1600E: DCM_X1Y3
XC3S250E, XC3S500E: DCM_X1Y1
XC3S1200E, XC3S1600E: DCM_X2Y3
H
G
F
E
Clock Line (see Table 41)
D
C
B
A
Bottom Left DCM
XC3S100: N/A
Bottom Right DCM
XC3S100: DCM_X0Y0
XC3S250E, XC3S500E: DCM_X0Y0
XC3S1200E, XC3S1600E: DCM_X1Y0
XC3S250E, XC3S500E: DCM_X1Y0
XC3S1200E, XC3S1600E: DCM_X2Y0
GCLK12 GCLK13 GCLK14 GCLK15
GCLK0
GCLK1
GCLK2
GCLK3
Associated Global Buffers
Differential Pair
Differential Pair
Differential Pair
Differential Pair
Package
P
N
P
N
P
N
P
N
Pin Number for Single-Ended Input
Pin Number for Single-Ended Input
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
P32
M4
P33
N4
P35
M5
P36
N5
P38
M6
P39
N6
P40
P6
P41
P7
P50
P74
M8
P51
P75
L8
P53
P77
N8
P54
P78
P8
P56
P80
T9
P57
P81
R9
P58
P82
P9
P59
P83
N9
N9
M9
U9
V9
U10
P11
R12
T10
P12
P12
R10
V10
Y12
P10
V11
W12
W9
V11
W10
U11
R10
R11
P10
T11
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
50
XILINX [ XILINX, INC ]
