Spartan-3E FPGA Family: Functional Description
Block RAM Attribute Definitions
A block RAM has a number of attributes that control its
behavior as shown in Table 24.
Table 24: Block RAM Attributes
Function
Attribute
Possible Values
Initial Content for Data Memory, Loaded during
Configuration
INITxx
(INIT_00 through INIT3F)
Each initialization string defines 32 hex values of the
16384-bit data memory of the block RAM.
Initial Content for Parity Memory, Loaded
during Configuration
INITPxx
Each initialization string defines 32 hex values of the
(INITP_00 through INITP0F) 2048-bit parity data memory of the block RAM.
Data Output Latch Initialization
INIT(single-port)
INITA, INITB(dual-port)
Hex value the width of the chosen port.
Hex value the width of the chosen port.
WRITE_FIRST, READ_FIRST, NO_CHANGE
Data Output Latch Synchronous Set/Reset
Value
SRVAL(single-port)
SRVAL_A, SRVAL_B(dual-port)
Data Output Latch Behavior during Write (see
Block RAM Data Operations)
WRITE_MODE
The waveforms for the write operation are shown in the top
half of Figure 33, Figure 34, and Figure 35. When the WE
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports. Table 25 describes the data
operations of each port as a result of the block RAM control
signals in their default active-High edges.
Table 25: Block RAM Function Table
Input Signals
Output Signals
RAM Data
Parity
GSR
EN
SSR
WE
CLK
ADDR
DIP
DI
DOP
DO
Data
Immediately After Configuration
Loaded During Configuration
X
X
INITP_xx
No Chg
No Chg
No Chg
INIT_xx
No Chg
No Chg
No Chg
Global Set/Reset Immediately After Configuration
1
0
0
0
X
0
1
1
X
X
1
X
X
0
X
X
↑
↑
X
X
X
X
X
INIT
RAM Disabled
No Chg
INIT
X
X
No Chg
SRVAL
Synchronous Set/Reset
SRVAL
X
X
Synchronous Set/Reset During Write RAM
1
1
addr
pdata Data
SRVAL
SRVAL
RAM(addr)
← pdata
RAM(addr)
← data
Read RAM, no Write Operation
RAM(pdata)
0
0
1
1
0
0
0
1
↑
↑
addr
X
X
RAM(data)
No Chg
No Chg
Write RAM, Simultaneous Read Operation
addr pdata Data WRITE_MODE = WRITE_FIRST
pdata
RAM(data)
No Chg
data
RAM(addr)
← pdata
RAM(addr)
← data
WRITE_MODE = READ_FIRST
RAM(data)
RAM(addr)
← pdata
RAM(addr)
← pdata
WRITE_MODE = NO_CHANGE
No Chg
RAM(addr)
← pdata
RAM(addr)
← pdata
DS312 (v4.2) December 14, 2018
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Product Specification
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