R
Functional Description
Table 55: Slave Parallel Mode Connections (Continued)
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
CSO_B
Output
Chip Select Output. Active Low.
Not used in single FPGA
applications. In a daisy-chain
configuration, this pin connects
to the CSI_B pin of the next
FPGA in the chain. Actively
drives.
INIT_B
Open-drain
InitializationIndicator. ActiveLow. Active during configuration. If
User I/O
bidirectional I/O Goes Low at start of configuration
during Initialization memory
CRC error detected during
configuration, FPGA drives
INIT_B Low.
clearing process. Released at end
of memory clearing, when mode
select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
DONE
Open-drain
FPGA Configuration Done. Low
Low indicates that the FPGA is
not yet configured.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
bidirectional I/O during configuration. Goes High
when FPGA successfully
completes configuration. Requires
external 330 Ω pull-up resistor to
2.5V.
PROG_B
Input
Program FPGA. Active Low. When Must be High to allow
Drive PROG_B Low and
release to reprogram
FPGA.
asserted Low for 300 ns or longer,
forces the FPGA to restart its
configuration to start.
configuration process by clearing
configuration memory and resetting
the DONE and INIT_B pins once
PROG_B returns High. Requires
external 4.7 kΩ pull-up resistor to
2.5V. If driving externally, use an
open-drain or open-collector driver.
Voltage Compatibility
Daisy-Chaining
V
Most Slave Parallel interface signals are within the
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain.
Use Slave Parallel mode (M[2:0] = <1:1:0>) for all FPGAs in
the daisy-chain. The schematic in Figure 59 is optimized for
FPGA downloading and does not support the SelectMAP
read interface. The FPGA’s RDWR_B pin must be Low dur-
ing configuration.
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 1.8V, 2.5V, or 3.3V to match
the requirements of the external host, ideally 2.5V. Using
1.8V or 3.3V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
2.5V VCCAUX supply. See application note XAPP453: "The
3.3V Configuration of Spartan-3 FPGAs" for additional infor-
mation.
After the lead FPGA is filled with its configuration data, the
lead FPGA enables the next FPGA in the daisy-chain by
asserting is chip-select output, CSO_B.
The LDC[2:0] and HDC signal are active in I/O Bank 1 but
are not used in the interface. Consequently, VCCO_1 can
be set the appropriate voltage for the application.
82
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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