R
Functional Description
CCLK
D[7:0]
+1.2V
+1.2V
V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_0
VCCO_1
I
VCC
VCCO_1
LDC0
V
VCCO_1
LDC0
LDC1
HDC
CE#
x8 or
x8/x16
Flash
PROM
LDC1
OE#
HDC
WE#
BYTE#
LDC2
LDC2
Not available
in VQ100
package
D
A[16:0]
Slave
Parallel
Mode
DQ[15:7]
BPI Mode
VCCO_2
D[7:0]
VCCO_2
D[7:0]
V
V
‘0’
‘1’
A
M2
M1
M0
DQ[7:0]
A[n:0]
‘1’
‘1’
‘0’
M2
M1
M0
A[23:17]
GND
Spartan-3E
FPGA
Spartan-3E
FPGA
BUSY
CCLK
BUSY
CCLK
‘0’
CSI_B
CSO_B
INIT_B
CSI_B
CSO_B
INIT_B
CSO_B
‘0’
RDWR_B
‘0’
RDWR_B
2.5V
JTAG
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TDI
TMS
TMS
TCK
TMS
TCK
TCK
V
+2.5V
TDO
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_50_021405
Figure 56: Daisy-Chaining from BPI Flash Mode
In-System Programming Support
Dynamically Loading Multiple Configuration
Images Using MultiBoot Option
I
In a production application, the parallel Flash PROM is
usually preprogrammed before it is mounted on the printed
circuit board. In-system programming support is available
from third-party boundary-scan tool vendors and from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the parallel Flash signals,
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the parallel Flash, in high-impedance (Hi-Z). If
the HSWAP input is High, the I/Os have pull-up resistors to
the VCCO input on their respective I/O bank. The external
programming hardware then has direct access to the paral-
lel Flash pins. The programming access points are high-
lighted in the gray boxes in Figure 55 and Figure 56.
After the FPGA configures itself using BPI mode from one
end of the parallel Flash PROM, then the FPGA can trigger
a MultiBoot event and reconfigure itself from the opposite
end of the parallel Flash PROM. MultiBoot is only available
when using BPI mode and only for applications with a single
Spartan-3E FPGA.
By default, MultiBoot mode is disabled. To trigger a Multi-
Boot event, assert a Low pulse lasting at least 300 ns on the
MultiBoot Trigger (MBT) input to the STARTUP_SPARTAN3E
library primitive. Figure 57 shows an example usage. At
power up, the FPGA loads itself from the attached parallel
Flash PROM. In this example, the M0 mode pin is Low so
the FPGA starts at address 0 and increments through the
Flash PROM memory locations. After the FPGA completes
configuration, the application loaded into the FPGA per-
forms a board-level or system test using FPGA logic. If the
test is successful, the FPGA triggers a MultiBoot event,
causing the FPGA to reconfigure from the opposite end of
the Flash PROM memory. This second configuration con-
tains the FPGA application for normal operation.
The FPGA itself can also be used as a parallel Flash PROM
programmer during development and test phases. Initially,
an FPGA-based programmer is downloaded into the FPGA
via JTAG. Then the FPGA performs the Flash PROM pro-
gramming algorithms and receives programming data from
the host via the FPGA’s JTAG interface. See Chapter 11 in
"Embedded System Tools Reference Manual".
78
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
