R
Functional Description
CCLK
+1.2V
+1.2V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_0
VCCO_2
VCCO_2
V
VCCO_2
Slave
Serial
Mode
Slave
Serial
Mode
V
‘1’
‘1’
‘1’
M2
M1
M0
‘1’
‘1’
‘1’
M2
M1
M0
Intelligent
Download Host
V
VCC
Spartan-3E
FPGA
Spartan-3E
FPGA
Configuration
Memory
Source
CLOCK
CCLK
DIN
CCLK
DIN
SERIAL_OUT
PROG_B
DONE
DOUT
DOUT
DOUT
INIT_B
INIT_B
•
•
•
•
Internal memory
Disk drive
Over network
Over RF link
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
INIT_B
TDI
TDI
GND
TMS
TCK
TMS
TCK
+2.5V
•
•
•
•
Microcontroller
Processor
Tester
PROG_B
DONE
PROG_B
DONE
GND
GND
Computer
PROG_B
PROG_B
DONE
Recommend
open-drain
driver
INIT_B
+2.5V
JTAG
TDI
TMS
TCK
TDO
TMS
TCK
DS312-2_55_022305
Figure 61: Daisy-Chaining using Slave Serial Mode
other configuration modes. No other pins are required as
part of the configuration interface.
JTAG Mode
The Spartan-3E FPGA has a dedicated four-wire IEEE
1149.1/1532 JTAG port that is always available any time the
FPGA is powered and regardless of the mode pin settings.
However, when the FPGA mode pins are set for JTAG mode
(M[2:0] = <1:0:1>), the FPGA waits to be configured via the
JTAG port after a power-on event or when PROG_B is
asserted. Selecting the JTAG mode simply disables the
Figure 62 illustrates a JTAG-only configuration interface.
The JTAG interface is easily cascaded to any number of
FPGAs by connecting the TDO output of one device to the
TDI input of the next device in the chain. The TDO output of
the last device in the chain loops back to the port connector.
86
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
