R
Functional Description
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Alternatively, the
bidirectional SelectMAP configuration interface is available
after configuration. To continue using SelectMAP mode, set
the Persist bitstream generator option to Yes. The external
host can then read and verify configuration data.
The Slave Parallel mode is also used with BPI mode to cre-
ate multi-FPGA daisy-chains. The lead FPGA is set for BPI
mode configuration; all the downstream daisy-chain FPGAs
are set for Slave Parallel configuration, as highlighted in
Figure 56.
Table 55: Slave Parallel Mode Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
HSWAP
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank VCCO input.
Drive at valid logic level
throughout configuration.
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
D[7:0]
Input
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 1, M1 = 1, M0 = 0 Sampled User I/O
when INIT_B goes High.
Data Input.
Byte-wide data provided by host. User I/O. If bitstream
FPGA captures data on rising
CCLK edge.
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
BUSY
Output
Busy Indicator.
If CCLK frequency is < 50 MHz,
this pin may be ignored. When
User I/O. If bitstream
option Persist=Yes,
High, indicates that the FPGA is becomes part of
not ready to receive additional
configuration data. Host must
hold data an additional clock
cycle.
SelectMap parallel
peripheral interface.
CSI_B
Input
Input
Input
Chip Select Input. Active Low.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
RDWR_B
CCLK
Read/Write Control. Active Low
write enable.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
Configuration Clock. If CCLK
PCB trace is long or has multiple
connections, terminate this output
to maintain signal integrity.
External clock.
User I/O If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
LDC[2:0]
HDC
Output
Output
Low During Configuration.
High During Configuration.
These pins are not used during
configuration. Low throughout
configuration.
User I/O
This pin is not used during
configuration. High throughout
configuration.
User I/O
DS312-2 (v1.1) March 21, 2005
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Advance Product Specification
XILINX [ XILINX, INC ]
