R
Functional Description
+1.2V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCO_2
V
Slave
Serial
Mode
V
‘1’
‘1’
‘1’
M2
M1
M0
Intelligent
Download Host
V
VCC
Spartan-3E
FPGA
Configuration
Memory
CLOCK
CCLK
DIN
Source
SERIAL_OUT
PROG_B
DONE
DOUT
INIT_B
• Internal memory
• Disk drive
VCCAUX
TDO
+2.5V
INIT_B
TDI
• Over network
• Over RF link
GND
TMS
TCK
+2.5V
• Microcontroller
• Processor
• Tester
PROG_B
DONE
GND
• Computer
PROG_B
Recommend
open-drain
driver
+2.5V
JTAG
TDI
TMS
TCK
TDO
DS312-2_54_022305
Figure 60: Slave Serial Configuration
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are avail-
able as full-featured user-I/O pins.
Similarly, the FPGA’s HSWAP pin must be Low to
P
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
84
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
