R
Functional Description
+1.2V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCO_1
VCCO_1
LDC0
LDC1
HDC
Slave
Parallel
Mode
LDC2
VCCO_2
V
V
‘1’
‘1’
‘0’
M2
M1
M0
Intelligent
Download Host
V
VCC
Spartan-3E
FPGA
D[7:0]
D[7:0]
BUSY
CSI_B
Configuration
Memory
Source
BUSY
SELECT
CSO_B
INIT_B
READ/WRITE
CLOCK
RDWR_B
CCLK
• Internal memory
• Disk drive
PROG_B
DONE
• Over network
• Over RF link
VCCAUX
TDO
+2.5V
INIT_B
TDI
TMS
TCK
GND
+2.5V
• Microcontroller
• Processor
• Tester
PROG_B
DONE
GND
• Computer
PROG_B
Recommend
open-drain +2.5V
driver
JTAG
TDI
TMS
TCK
TDO
DS312-2_52_022205
Figure 58: Slave Parallel Configuration Mode
The external download host starts the configuration process
by pulsing PROG_B and monitoring that the INIT_B pin
goes High, indicating that the FPGA is ready to receive its
first data. The host asserts the active-Low chip-select signal
(CSI_B) and the active-Low Write signal (RDWR_B). The
host then continues supplying data and clock signals until
either the FPGA’s DONE pin goes High, indicating a suc-
cessful configuration, or until the FPGA’s INIT_B pin goes
Low, indicating a configuration error.
is 50 MHz or below, the BUSY pin may be ignored but
actively drives during configuration.
The configuration process requires more clock cycles than
indicated from the configuration file size. Additional clocks
are required during the FPGA’s start-up sequence, espe-
cially if the FPGA is programmed to wait for selected Digital
Clock Managers (DCMs) to lock to their respective clock
inputs (see Start-Up, page 91).
If the Slave Parallel interface is only used to configure the
FPGA, never to read data back, then the RDWR_B signal
can also be eliminated from the interface. However,
RDWR_B must remain Low during configuration.
The FPGA captures data on the rising CCLK edge. If the
CCLK frequency exceeds 50 MHz, then the host must also
monitor the FPGA’s BUSY output. If the FPGA asserts
BUSY High, the host must hold the data for an additional
clock cycle, until BUSY returns Low. If the CCLK frequency
80
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
