R
Functional Description
Table 56: Slave Serial Mode Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
HSWAP
Input
User I/O Pull-Up Control. When Drive at valid logic level
Low during configuration, enables throughout configuration.
pull-up resistors in all I/O pins to
User I/O
respective I/O bank VCCO input.
0: Pull-up during configuration
1: No pull-ups
M[2:0]
DIN
Input
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 1, M1 = 1, M0 = 1 Sampled User I/O
when INIT_B goes High.
Data Input.
Serial data provided by host.
FPGA captures data on rising
CCLK edge.
User I/O
User I/O
CCLK
Input
Configuration Clock. If CCLK
PCB trace is long or has multiple
connections, terminate this output
to maintain signal integrity.
External clock.
INIT_B
Open-drain
Initialization Indicator. Active
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
User I/O
bidirectional I/O Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
DONE
Open-drain
FPGA Configuration Done. Low Low indicates that the FPGA is
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
bidirectional I/O during configuration. Goes High
when FPGA successfully
not yet configured.
completes configuration.
Requires external 330 Ω pull-up
resistor to 2.5V.
PROG_B
Input
Program FPGA. Active Low.
Must be High to allow
Drive PROG_B Low and
release to reprogram
FPGA.
When asserted Low for 300 ns or configuration to start.
longer, forces the FPGA to restart
its configuration process by
clearing configuration memory
and resetting the DONE and
INIT_B pins once PROG_B
returns High. Requires external
4.7 kΩ pull-up resistor to 2.5V. If
driving externally, use an
open-drain or open-collector
driver.
Voltage Compatibility
Daisy-Chaining
V
Most Slave Serial interface signals are within the
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 61. Use Slave Serial mode
(M[2:0] = <1:1:1>) for all FPGAs in the daisy-chain. After
the lead FPGA is filled with its configuration data, the lead
FPGA passes configuration data via its DOUT output pin to
the next FPGA on the falling CCLK edge.
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 3.3V, 2.5V, or 1.8V to match
the requirements of the external host, ideally 2.5V. Using
3.3V or 1.8V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
2.5V VCCAUX supply. See application note XAPP453: "The
3.3V Configuration of Spartan-3 FPGAs" for additional infor-
mation.
DS312-2 (v1.1) March 21, 2005
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Advance Product Specification
XILINX [ XILINX, INC ]
