R
Functional Description
Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
A[23:0]
Output
Address
Connect to PROM address
inputs. High order address lines
may not be available in all
packages and not all may be
required. Number of address
lines required depends on the
size of the attached Flash PROM.
FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
Only 20 address lines are
available in TQ144 package.
D[7:0]
CSO_B
BUSY
CCLK
Input
Data Input
FPGA receives byte-wide data on User I/O If bitstream
these pins in response the
address presented on A[23:0].
Data captured by FPGA
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
Output
Output
Output
Chip Select Output. Active Low.
Not used in single FPGA
User I/O
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. Actively drives.
Busy Indicator. Typically only
used after configuration, if
bitstream option Persist=Yes.
Not used during configuration but User I/O. If bitstream
actively drives.
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
Configuration Clock. Generated Not used in single FPGA
User I/O If bitstream
by FPGA internal oscillator.
Frequency controlled by
applications but actively drives. In option Persist=Yes,
a daisy-chain configuration, becomes part of
drives the CCLK inputs of all other SelectMap parallel
ConfigRate bitstream generator
option. If CCLK PCB trace is long
or has multiple connections,
terminate this output to maintain
signal integrity.
FPGAs in the daisy-chain.
peripheral interface.
INIT_B
Open-drain
Initialization Indicator. Active
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
User I/O
bidirectional I/O Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
74
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
