R
Functional Description
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
actively drives during configuration and is available as a
user I/O after configuration.
The RDWR_B and CSI_B must be Low throughout the con-
figuration process. After configuration, these pins also
become user I/O.
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Furthermore, the
bidirectional SelectMAP configuration peripheral interface
(see Slave Parallel Mode) is available after configuration.
To continue using SelectMAP mode, set the Persist bit-
stream generator option to Yes. An external host can then
read and verify configuration data.
In a single-FPGA application, the FPGA’s CSO_B and
CCLK pins are not used but are actively driving during the
configuration process. The BUSY pin is not used but also
Table 51: Byte-Wide Peripheral Interface (BPI) Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
Input
User I/O Pull-Up Control. When
Drive at valid logic level
HSWAP
Low during configuration, enables throughout configuration.
pull-up resistors in all I/O pins to
P
respective I/O bank VCCO input.
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 0, M1 = 1. Set M0 = 0 to
start at address 0, increment
addresses. Set M0 = 1 to start at
address 0xFFFFFF and
User I/O
A
decrement addresses. Sampled
when INIT_B goes High.
CSI_B
Input
Input
Chip Select Input. Active Low.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
RDWR_B
Read/Write Control. Active Low
write enable. Read functionality
typically only used after
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
configuration, if bitstream option
Persist=Yes.
SelectMap parallel
peripheral interface.
LDC0
LDC1
HDC
Output
Output
Output
Output
PROM Chip Enable
PROM Output Enable
PROM Write Enable
PROM Byte Mode
Connect to PROM chip-select
input (CE#). FPGA drives this
signal Low throughout
configuration.
User I/O
Connect to PROM output-enable User I/O
input (OE#). FPGA drives this
signal Low throughout
configuration.
Connect to PROM write-enable
input (WE#). FPGA drives this
signal High throughout
configuration.
User I/O
LDC2
D
This signal is not used for x8
PROMs. For PROMs with a
x8/x16 data width control,
connect to PROM byte-mode
input (BYTE#). See Precautions
Using x8/x16 Flash PROMs.
FPGA drives this signal Low
throughout configuration.
User I/O. Drive this pin
High after configuration to
use a x8/x16 PROM in
x16 mode.
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
73
Advance Product Specification
XILINX [ XILINX, INC ]
