R
Functional Description
CCLK
+1.2V
+1.2V
+3.3V
SPI
Serial
Flash
VCCINT
VCCINT
P
P
HSWAP
VCCO_0
VCCO_0
+3.3V
P
HSWAP
VCCO_0
VCCO_0
+3.3V
I
VCC
DATA_IN
VCCO_2
MOSI
VCCO_2
Slave
Serial
Mode
SPI Mode
DIN
DATA_OUT
SELECT
‘0’
‘0’
‘1’
M2
M1
M0
CSO_B
‘1’
‘1’
‘1’
M2
M1
M0
W
WR_PROTECT
HOLD
‘1’
CLOCK
Variant Select
Spartan-3E
FPGA
Spartan-3E
FPGA
GND
‘1’
S
VS2
VS1
VS0
‘1’
CCLK
CCLK
DIN
DOUT
INIT_B
DOUT
DOUT
INIT_B
+2.5V
JTAG
TDI
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TMS
TCK
TDO
TMS
TCK
TMS
TCK
+2.5V
+3.3V
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_48_021405
Figure 54: Daisy-Chaining from SPI Flash Mode
to a 24-bit address lines to access an attached parallel
Flash. Only 20 address lines are generated for Spartan-3E
FPGAs in the TQ144 package. The BPI mode is not avail-
able for Spartan-3E FPGAs in the VQ100 package.
In-System Programming Support
I
In a production application, the SPI Flash PROM is usu-
ally pre-programmed before it is mounted on the printed cir-
cuit board. In-system programming support is available
from some third-party PROM programmers using a socket
adapter with attached wires. To gain access to the SPI
Flash signals, drive the FPGA’s PROG_B input Low with an
open-drain driver. This action places all FPGA I/O pins,
including those attached to the SPI Flash, in high-imped-
ance (Hi-Z). If the HSWAP input is High, the I/Os have
pull-up resistors to the VCCO input on their respective I/O
bank. The external programming hardware then has direct
access to the SPI Flash pins. The programming access
points are highlighted in the gray box in Figure 50,
Figure 51, and Figure 54.
The interface is designed for standard parallel NOR Flash
PROMs and supports both byte-wide (x8) and
byte-wide/halfword (x8/x16) PROMs. The interface does not
support halfword-only (x16) PROMs. The interface works
equally wells with other memories that use a similar inter-
face such as SRAM, NVRAM, EEPROM, EPROM, or
masked ROM but is primarily designed for Flash memory.
There is another type of Flash memory called NAND Flash,
which is commonly used in memory cards for digital cam-
eras, etc. Spartan-3E FPGAs do not configure directly from
NAND Flash memories.
The FPGA’s internal oscillator controls the interface timing
and the FPGA supplies the clock on the CCLK output pin.
However, the CCLK signal is not used in single FPGA appli-
cations. Similarly, the FPGA drives three pins Low during
configuration (LDC[2:0]) and one pin High during configura-
tion (HDC) to the PROM’s control inputs.
Byte-Wide Peripheral Interface (BPI) Parallel
Flash Mode
In
Byte-wide
Peripheral
Interface
(BPI)
mode
(M[2:0] = <0:1:0> or <0:1:1>), a Spartan-3E FPGA config-
ures itself from an industry-standard parallel NOR Flash
PROM, as illustrated in Figure 55. The FPGA generates up
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
71
Advance Product Specification
XILINX [ XILINX, INC ]
