R
Functional Description
ious values as described in Table 26. The basic frequency
synthesis outputs are described in Table 25.
2. The fCLKFX frequency calculated from the above
expression accords with the DCM’s operating frequency
specifications.
Duty Cycle Correction of DLL Clock Outputs
For example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE
= 3, then the frequency of the output clock signal is 5/3 that
of the input clock signal.
The CLK2X(1), CLK2X180, and CLKDV(2) output signals
ordinarily exhibit a 50% duty cycle – even if the incoming
CLKIN signal has a different duty cycle. Fifty-percent duty
cycle means that the High and Low times of each clock
cycle are equal. The DUTY_CYCLE_CORRECTION
attribute determines whether or not duty cycle correction is
applied to the CLK0, CLK90, CLK180, and CLK270 outputs.
If DUTY_CYCLE_CORRECTION is set to TRUE, then the
duty cycle of these four outputs is corrected to 50%. If
DUTY_CYCLE_CORRECTION is set to FALSE, then these
outputs exhibit the same duty cycle as the CLKIN signal.
Figure 40 compares the characteristics of the DLL’s output
signals to those of the CLKIN signal.
0o 90o 180o 270o 0o 90o 180o 270o 0o
Phase:
Input Signal (30% Duty Cycle)
t
CLKIN
Output Signal - Duty Cycle is Always Corrected
The CLK2X output generates a 25% duty cycle clock at the
same frequency as the CLKIN signal until the DLL has
achieved lock.
CLK2X
The duty cycle of the CLKDV outputs may differ somewhat
from 50% (i.e., the signal is High for less than 50% of the
period) when the CLKDV_DIVIDE attribute is set to a
non-integer value and the DLL is operating in the High Fre-
quency mode.
CLK2X180
(1)
CLKDV
Output Signal - Attribute Corrects Duty Cycle
Digital Frequency Synthesizer (DFS)
DUTY_CYCLE_CORRECTION = FALSE
The DFS component generates clock signals the frequency
of which is a product of the clock frequency at the CLKIN
input and a ratio of two user-determined integers. Because
of the wide range of possible output frequencies such a ratio
permits, the DFS feature provides still further flexibility than
the DLL’s basic synthesis options as described in the pre-
ceding section. The DFS component’s two dedicated out-
puts, CLKFX and CLKFX180, are defined in Table 28.
CLK0
CLK90
CLK180
CLK270
The signal at the CLKFX180 output is essentially an inver-
sion of the CLKFX signal. These two outputs always exhibit
a 50% duty cycle. This is true even when the CLKIN signal
does not. These DFS clock outputs are driven at the same
time as the DLL’s seven clock outputs.
DUTY_CYCLE_CORRECTION = TRUE
CLK0
The numerator of the ratio is the integer value assigned to
the attribute CLKFX_MULTIPLY and the denominator is the
integer value assigned to the attribute CLKFX_DIVIDE.
These attributes are described in Table 27.
CLK90
CLK180
The output frequency (fCLKFX) can be expressed as a func-
tion of the incoming clock frequency (fCLKIN) as follows:
CLK270
fCLKFX = fCLKIN*(CLKFX_MULTIPLY/CLKFX_DIVIDE) (3)
DS099-2_10_031303
Regarding the two attributes, it is possible to assign any
combination of integer values, provided that two conditions
are met:
Figure 40: Characteristics of the DLL Clock Outputs
DFS With or Without the DLL
1. The two values fall within their corresponding ranges,
as specified in Table 27.
The DFS component can be used with or without the DLL
component: Without the DLL, the DFS component multi-
plies or divides the CLKIN signal frequency according to the
respective CLKFX_MULTIPLY and CLKFX_DIVIDE values,
DS312-2 (v1.1) March 21, 2005
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Advance Product Specification
XILINX [ XILINX, INC ]
