R
Functional Description
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
Delay
1
Delay
2
Delay
n-1
Delay
n
CLKIN
Control
LOCKED
Phase
Detection
CLKFB
RST
DS099-2_08_041103
Figure 38: Simplified Functional Diagram of DLL
Table 25: DLL Signals
Signal
CLKIN
Direction
Input
Description
Accepts original clock signal.
CLKFB
Input
Accepts either CLK0 or CLK2X as the feedback signal. (Set CLK_FEEDBACK attribute
accordingly).
CLK0
Output
Output
Output
Output
Output
Output
Generates a clock signal with same frequency and phase as CLKIN.
CLK90
Generates a clock signal with same frequency as CLKIN, only phase-shifted 90°.
Generates a clock signal with same frequency as CLKIN, only phase-shifted 180°.
Generates a clock signal with same frequency as CLKIN, only phase-shifted 270°.
Generates a clock signal with same phase as CLKIN, only twice the frequency.
CLK180
CLK270
CLK2X
CLK2X180
Generates a clock signal with twice the frequency of CLKIN, phase-shifted 180° with
respect to CLKIN.
CLKDV
Output
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency
clock signal that is phase-aligned to CLKIN.
neously. Signals that initialize and report the state of the
DLL are discussed in the Status Logic Component section.
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to elimi-
nate clock skew. The main signal path of the DLL consists of
an input stage, followed by a series of discrete delay ele-
ments or taps, which in turn leads to an output stage. This
path together with logic for phase detection and control
forms a system complete with feedback as shown in
Figure 38. In Spartan-3E FPGAs, the DLL is implemented
using a counter-based delay line.
The clock signal supplied to the CLKIN input serves as a
reference waveform. The DLL seeks to align the rising-edge
of feedback signal at the CLKFB input with the rising-edge
of CLKIN input. When eliminating clock skew, the common
approach to using the DLL is as follows: The CLK0 signal is
passed through the clock distribution network to all the reg-
isters it synchronizes. These registers are either internal or
external to the FPGA. After passing through the clock distri-
bution network, the clock signal returns to the DLL via a
feedback line called CLKFB. The control block inside the
DLL measures the phase error between CLKFB and CLKIN.
The DLL component has two clock inputs, CLKIN and
CLKFB, as well as seven clock outputs, CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as
described in Table 25. The clock outputs drive simulta-
40
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
