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XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
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R
Functional Description  
a. CLKOUT_PHASE_SHIFT = NONE  
CLKIN  
CLKFB  
b. CLKOUT_PHASE_SHIFT = FIXED  
CLKIN  
0
–255  
+255  
Shift Range over all P Values:  
CLKFB  
P
512  
* T  
CLKIN  
c. CLKOUT_PHASE_SHIFT = VARIABLE  
CLKIN  
–255  
+255  
0
Shift Range over all P Values:  
P
512  
* T  
CLKIN  
CLKFB before  
Increment  
Shift Range over all N Values:  
N
512  
* T  
CLKIN  
CLKFB after  
Increment  
DS312-2_61_021505  
Figure 41: Phase Shifter Waveforms  
nent (PSEN, PSCLK, and PSINCDEC), as defined in  
Table 30.  
The Variable Phase Mode  
The Variable Phase mode dynamically adjusts the fine  
phase shift over time using three inputs to the PS compo-  
Table 30: Signals for Variable Phase Mode  
Signal  
PSEN(1)  
Direction  
Input  
Description  
Enables PSCLK for variable phase adjustment.  
PSCLK(1)  
Input  
Input  
Clock to synchronize phase shift adjustment.  
PSINCDEC(1)  
Chooses between increment and decrement for phase adjustment. It is  
synchronized to the PSCLK signal.  
PSDONE  
Output  
Goes High to indicate that present phase adjustment is complete and PS component  
is ready for next phase adjustment request. It is synchronized to the PSCLK signal.  
Notes:  
1. It is possible to program this input for either a true or inverted polarity.  
46  
www.xilinx.com  
DS312-2 (v1.1) March 21, 2005  
Advance Product Specification  
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