R
Functional Description
This phase error is a measure of the clock skew that the
clock distribution network introduces. The control block acti-
vates the appropriate number of delay elements to cancel
out the clock skew. Once the DLL has brought the CLK0 sig-
nal in phase with the CLKIN signal, it asserts the LOCKED
output, indicating a lock on to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the
DLL component through the use of the attributes described
in Table 26. Each attribute is described in detail in the sec-
tions that follow:
Table 26: DLL Attributes
Attribute
CLK_FEEDBACK
Description
Chooses either the CLK0 or CLK2X output to NONE, 1X, 2X
Values
drive the CLKFB input
CLKIN_DIVIDE_BY_2
CLKDV_DIVIDE
Halves the frequency of the CLKIN signal just TRUE, FALSE
as it enters the DCM
Selects the constant used to divide the CLKIN 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0,
input frequency to generate the CLKDV
output frequency
6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14,
15, and 16
DUTY_CYCLE_CORRECTION Enables 50% duty cycle correction for the
CLK0, CLK90, CLK180, and CLK270 outputs
TRUE, FALSE
The feedback loop is essential for DLL operation and is
established by driving the CLKFB input with either the CLK0
or the CLK2X signal so that any undesirable clock distribu-
tion delay is included in the loop. It is possible to use either
of these two signals for synchronizing any of the seven DLL
outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X,
or CLK2X180. The value assigned to the CLK_FEEDBACK
attribute must agree with the physical feedback connection:
a value of 1X for the CLK0 case, 2X for the CLK2X case. If
the DCM is used in an application that does not require the
DLL — that is, only the DFS is used — then there is no
required feedback loop so CLK_FEEDBACK is set to
NONE.
DLL Clock Input Connections
An external clock source enters the FPGA using a Global
Clock Input Buffer (IBUFG), which directly accesses the glo-
bal clock network or via an Input Buffer (IBUF). Clock sig-
nals within the FPGA drive a global clock net using a Global
Clock Multiplexer Buffer (BUFGMUX). The global clock net
connects directly to the CLKIN input. The internal and exter-
nal connections are shown in Figure 39a and Figure 39c,
respectively. A differential clock (e.g., LVDS) can serve as
an input to CLKIN.
DLL Clock Output and Feedback Connections
As many as four of the nine DCM clock outputs can simulta-
neously drive four of the BUFGMUX buffers on the same die
edge. All DCM clock outputs can simultaneously drive gen-
eral routing resources, including interconnect leading to
OBUF buffers.
There are two basic cases that determine how to connect
the DLL clock outputs and feedback connections: on-chip
synchronization and off-chip synchronization, which are
illustrated in Figure 39a through Figure 39d.
DS312-2 (v1.1) March 21, 2005
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Advance Product Specification
XILINX [ XILINX, INC ]
