R
Functional Description
Just following device configuration, the PS component ini-
tially determines TPS by evaluating Equation (4) for the
value assigned to the PHASE_SHIFT attribute. Then to
dynamically adjust that phase shift, use the three PS inputs
to increase or decrease the fine phase shift.
Asserting the Reset (RST) input, returns TPS to its original
shift time, as determined by the PHASE_SHIFT attribute
value. The set of waveforms in Figure 41c illustrates the
relationship between CLKFB and CLKIN in the Variable
Phase mode.
PSINCDEC is synchronized to the PSCLK clock signal,
which is enabled by asserting PSEN. It is possible to drive
the PSCLK input with the CLKIN signal or any other clock
signal. A request for phase adjustment is entered as follows:
For each PSCLK cycle that PSINCDEC is High, the PS
component adds 1/512 of a CLKIN cycle to TPS. Similarly,
for each enabled PSCLK cycle that PSINCDEC is Low, the
The Status Logic Component
The Status Logic component not only reports on the state of
the DCM but also provides a means of resetting the DCM to
an initial known state. The signals associated with the Sta-
tus Logic component are described in Table 31.
As a rule, the Reset (RST) input is asserted only upon con-
figuring the device or changing the CLKIN frequency. A
DCM reset does not affect attribute values (e.g.,
CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, tie
RST to GND.
PS component subtracts 1/512 of a CLKIN cycle from TPS
.
The phase adjustment may require as many as 100 CLKIN
cycles plus three PSCLK cycles to take effect, at which
point the output PSDONE goes High for one PSCLK cycle.
This pulse indicates that the PS component has finished the
present adjustment and is now ready for the next request.
The eight bits of the STATUS bus are defined in Table 32.
Table 31: Status Logic Signals
Signal
Direction
Input
Description
RST
A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for
a delay of zero. Sets the LOCKED output Low. This input is asynchronous.
STATUS[7:0]
LOCKED
Output
Output
The bit values on the STATUS bus provide information regarding the state of DLL and
PS operation
Indicates that the CLKIN and CLKFB signals are in phase by going High. The two
signals are out-of-phase when Low.
Table 32: DCM Status Bus
Bit
0
Name
Reserved
CLKIN Stopped
Description
-
1
A value of 1 indicates that the CLKIN input signal is not toggling. A value of 0 indicates toggling.
This bit functions only when the CLKFB input is connected.(1)
2
CLKFX Stopped A value of 1 indicates that the CLKFX output is not toggling. A value of 0 indicates toggling.
This bit functions only when the CLKFX or CLKFX180 output are connected.
3-6 Reserved
-
Notes:
1. If only the DFS clock outputs are used, but none of the DLL clock outputs, this bit does not go High when the CLKIN signal stops.
DS312-2 (v1.1) March 21, 2005
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Advance Product Specification
XILINX [ XILINX, INC ]
