R
Functional Description
generating a clock with the new target frequency on the
CLKFX and CLKFX180 outputs. Though classified as
belonging to the DLL component, the CLKIN input is shared
with the DFS component. This case does not employ feed-
back loop. Therefore, it cannot correct for clock distribution
delay.
DFS Clock Output Connections
There are two basic cases that determine how to connect
the DFS clock outputs: on-chip and off-chip, which are illus-
trated in Figure 39a and Figure 39c, respectively. This is
similar to what has already been described for the DLL com-
ponent. See DLL Clock Output and Feedback Connec-
tions.
With the DLL, the DFS operates as described in the preced-
ing case, only with the additional benefit of eliminating the
clock distribution delay. In this case, a feedback loop from
the CLK0 output to the CLKFB input must be present.
In the on-chip case, it is possible to connect either of the
DFS’s two output clock signals through general routing
resources to the FPGA’s internal registers. Either a Global
Clock Buffer (BUFG) or a BUFGMUX affords access to the
global clock network. The optional feedback loop is formed
in this way, routing CLK0 to a global clock net, which in turn
drives the CLKFB input.
The DLL and DFS components work together to achieve
this phase correction as follows: Given values for the
CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, the DLL
selects the delay element for which the output clock edge
coincides with the input clock edge whenever mathemati-
cally possible. For example, when CLKFX_MULTIPLY = 5
and CLKFX_DIVIDE = 3, the input and output clock edges
coincide every three input periods, which is equivalent in
time to five output periods.
In the off-chip case, the DFS’s two output clock signals, plus
CLK0 for an optional feedback loop, can exit the FPGA
using output buffers (OBUF) to drive a clock network plus
registers on the board. The feedback loop is formed by
feeding the CLK0 signal back into the FPGA using an
IBUFG, which directly accesses the global clock network, or
an IBUF. Then the global clock net is connected directly to
the CLKFB input.
Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values
achieve faster lock times. With no factors common to the
two attributes, alignment occurs once with every number of
cycles equal to the CLKFX_DIVIDE value. Therefore, it is
recommended that the user reduce these values by factor-
Phase Shifter (PS)
ing
wherever
possible.
For
example,
given
The DCM provides two approaches to controlling the phase
of a DCM clock output signal relative to the CLKIN signal:
First, there are nine clock outputs that employ the DLL to
achieve a desired phase relationship: CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, CLKDV CLKFX, and
CLKFX180. These outputs afford “coarse” phase control.
CLKFX_MULTIPLY = 9 and CLKFX_DIVIDE = 6, removing
a factor of three yields CLKFX_MULTIPLY = 3 and
CLKFX_DIVIDE = 2. While both value-pairs result in the
multiplication of clock frequency by 3/2, the latter value-pair
enables the DLL to lock more quickly.
The second approach uses the PS component described in
this section to provide a still finer degree of control. The PS
component accomplishes this by introducing a "fine phase
shift" (TPS) between the CLKFB and CLKIN signals inside
the DLL component. The user can control this fine phase
shift down to a resolution of 1/512 of a CLKIN cycle or one
tap delay (DCM_TAP), whichever is greater. When in use,
the PS component shifts the phase of all nine DCM clock
output signals together. If the PS component is used
together with a DCM clock output such as the CLK90,
CLK180, CLK270, CLK2X180, and CLKFX180, then the
fine phase shift of the former gets added to the coarse
phase shift of the latter.
Table 27: DFS Attributes
Attribute
Description
Values
CLKFX_MULTIPLY
Frequency
Integer from
2 to 32,
inclusive
multiplier
constant
CLKFX_DIVIDE
Frequency divisor Integer from
constant
1 to 32,
inclusive
Table 28: DFS Signals
Signal
Direction Description
PS Component Enabling and Mode Selection
CLKFX
Output
Multiplies the CLKIN frequency
by the attribute-value ratio
(CLKFX_MULTIPLY/
CLKFX_DIVIDE) to generate a
clock signal with a new target
frequency.
The CLKOUT_PHASE_SHIFT attribute enables the PS
component for use in addition to selecting between two
operating modes. As described in Table 29, this attribute
has three possible values: NONE, FIXED, and VARIABLE.
When CLKOUT_PHASE_SHIFT is set to NONE, the PS
component is disabled and its inputs, PSEN, PSCLK, and
PSINCDEC, must be tied to GND. The set of waveforms in
Figure 41a shows the disabled case, where the DLL main-
tains a zero-phase alignment of signals CLKFB and CLKIN
upon which the PS component has no effect. The PS com-
CLKFX180 Output
Generates a clock signal with
same frequency as CLKFX,
only shifted 180° out-of-phase.
44
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
