欢迎访问ic37.com |
会员登录 免费注册
发布采购

XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
 浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第42页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第43页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第44页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第45页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第47页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第48页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第49页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第50页  
R
Functional Description  
The DCM supports three major functions:  
Digital Clock Managers (DCMs)  
Clock-skew Elimination: Clock skew describes the  
Differences from the Spartan-3 Architecture  
extent to which clock signals may, under normal  
circumstances, deviate from zero-phase alignment. It  
occurs when slight differences in path delays cause the  
clock signal to arrive at different points on the die at  
different times. This clock skew can increase set-up  
and hold time requirements as well as clock-to-out  
time, which may be undesirable in applications  
operating at a high frequency, when timing is critical.  
The DCM eliminates clock skew by aligning the output  
clock signal it generates with another version of the  
clock signal that is fed back. As a result, the two clock  
signals establish a zero-phase relationship. This  
effectively cancels out clock distribution delays that  
might lie in the signal path leading from the clock  
Spartan-3E FPGAs have two, four, or eight DCMs,  
depending on device size.  
The Spartan-3E DCM has a maximum phase shift  
range of 180°. The Spartan-3 DCM range is 360°.  
The Spartan-3E DLL supports lower input frequencies,  
down to 5 MHz. Spartan-3 DLLs supports down to 24  
MHz.  
Overview  
Spartan-3E Digital Clock Managers (DCMs) provide flexi-  
ble, complete control over clock frequency, phase shift and  
skew. To accomplish this, the DCM employs a Delay-Locked  
Loop (DLL), a fully digital control system that uses feedback  
to maintain clock signal characteristics with a high degree of  
precision despite normal variations in operating tempera-  
ture and voltage. This section provides a fundamental  
description of the DCM. See XAPP462: "Using Digital Clock  
Managers (DCMs) in Spartan-3 Series FPGAs" for further  
information.  
output of the DCM to its feedback input.  
Frequency Synthesis: Provided with an input signal,  
the DCM can generate a wide range of different output  
clock frequencies. This is accomplished by either  
multiplying and/or dividing the frequency of the input  
clock signal by any of several different factors.  
Phase Shifting: The DCM provides the ability to shift  
the phase of all its output clock signals with respect to  
its input clock signal.  
The XC3S100E FPGA has two DCMs, one at the top and  
one at the bottom of the device. The XC3S250E and  
XC3S500E FPGAs each include four DCMs, two at the top  
and two at the bottom. The XC3S1200E and XC3S1600E  
FPGAs contain eight DCMs with two on each edge (see  
also Figure 42). The DCM in Spartan-3E FPGAs is sur-  
rounded by CLBs within the logic array and is no longer  
located at the top and bottom of a column of block RAM as  
in the Spartan-3 architecture,. The Digital Clock Manager is  
instantiated into a design as the “DCM” primitive.  
The DCM has four functional components: the  
Delay-Locked Loop (DLL), the Digital Frequency Synthe-  
sizer (DFS), the Phase Shifter (PS), and the Status Logic.  
Each component has its associated signals, as shown in  
Figure 37.  
DCM  
PSINCDEC  
Phase  
Shifter  
PSEN  
PSCLK  
PSDONE  
Clock  
CLK0  
Distribution  
CLKIN  
CLKFB  
CLK90  
Delay  
CLK180  
CLK270  
CLK2X  
CLK2X180  
CLKDV  
CLKFX  
DFS  
DLL  
CLKFX180  
LOCKED  
Status  
Logic  
RST  
8
STATUS [7:0]  
DS099-2_07_040103  
Figure 37: DCM Functional Blocks and Associated Signals  
DS312-2 (v1.1) March 21, 2005  
www.xilinx.com  
39  
Advance Product Specification