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XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
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Functional Description  
The MULT18X18SIO primitive has two additional ports  
called BCIN and BCOUT to cascade or share the multi-  
plier’s ‘B’ input among several multiplier bocks. The 18-bit  
BCIN "cascade" input port offers an alternate input source  
from the more typical ‘B’ input. The B_INPUT attribute spec-  
ifies whether the specific implementation uses the BCIN or  
‘B’ input path. Setting B_INPUT to DIRECT chooses the ‘B’  
input. Setting B_INPUT to CASCADE selects the alternate  
BCIN input. The BREG register then optionally holds the  
selected input value, if required.  
MULT18X18SIO  
A[17:0]  
B[17:0]  
CEA  
P[35:0]  
CEB  
CEP  
CLK  
RSTA  
RSTB  
RSTP  
BCIN[17:0]  
BCOUT is an 18-bit output port that always reflects the  
value that is applied to the multiplier’s second input, which is  
either the ‘B’ input, the cascaded value from the BCIN input,  
or the output of the BREG if it is inserted.  
BCOUT[17:0]  
DS312-2_28_021205  
Figure 35 illustrates the four possible configurations using  
different settings for the B_INPUT attribute and the BREG  
attribute.  
Figure 34: MULT18X18SIO Primitive  
BCOUT[17:0]  
BCOUT[17:0]  
BREG  
CE  
X
X
CEB  
D
Q
BREG = 0  
CLK  
B_INPUT = CASCADE  
RST  
BREG = 1  
B_INPUT = CASCADE  
RSTB  
BCIN[17:0]  
BCIN[17:0]  
BCOUT[17:0]  
BCOUT[17:0]  
BREG  
X
X
CEB  
CE  
D
B[17:0]  
B[17:0]  
Q
BREG = 0  
B_INPUT = DIRECT  
CLK  
RST  
BREG = 1  
B_INPUT = DIRECT  
RSTB  
DS312-2_29_021505  
Figure 35: Four Configurations of the B Input  
36  
www.xilinx.com  
DS312-2 (v1.1) March 21, 2005  
Advance Product Specification  
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