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XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
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Functional Description  
Implement multipliers with inputs less than 18 bits by  
sign-extending the inputs (i.e., replicating the most-signifi-  
cant bit). Wider multiplication operations are performed by  
combining the dedicated multipliers and slice-based logic in  
any viable combination or by time-sharing a single multi-  
plier. Perform unsigned multiplication by restricting the  
inputs to the positive range. Tie the most-significant bit Low  
and represent the unsigned value in the remaining 17  
lesser-significant bits.  
Dedicated Multipliers  
The Spartan-3E devices provide 4 to 36 dedicated multiplier  
blocks per device. The multipliers are located together with  
the block RAM in one or two columns depending on device  
density. See Arrangement of RAM Blocks on Die for  
details on the location of these blocks and their connectivity.  
The multiplier blocks primarily perform two’s complement  
numerical multiplication but can also perform some less  
obvious applications such as simple data storage and barrel  
shifting. Logic slices also implement efficient small multipli-  
ers and thereby supplement the dedicated multipliers. The  
Spartan-3E dedicated multiplier blocks have additional fea-  
tures beyond those provided in Spartan-3 FPGAs.  
As shown in Figure 33, each multiplier block has optional  
registers on each of the multiplier inputs and the output. The  
registers are named AREG, BREG, and PREG and can be  
used in any combination. The clock input is common to all  
the registers within a block, but each register has an inde-  
pendent clock enable and synchronous reset controls mak-  
ing them ideal for storing data samples and coefficients.  
When used for pipelining, the registers boost the multiplier  
clock rate, beneficial for higher performance applications.  
Each multiplier performs the principle operation P = A × B,  
where ‘A’ and ‘B’ are 18-bit words in two’s complement  
form, and ‘P’ is the full-precision 36-bit product, also in two’s  
complement form. The 18-bit inputs represent values rang-  
ing from -131,07210 to +131,07110 with a resulting product  
ranging from -17,179,738,11210 to +17,179,869,18410.  
Figure 33 illustrates the principle features of the multiplier  
block.  
AREG  
(Optional)  
CEA  
CE  
D
A[17:0]  
Q
PREG  
(Optional)  
RST  
CEP  
CE  
D
RSTA  
Q
P[35:0]  
X
BREG  
(Optional)  
RST  
CEB  
CE  
RSTP  
B[17:0]  
D
Q
RST  
RSTB  
CLK  
DS312-2_27_021205  
Figure 33: Principle Ports and Functions of Dedicated Multiplier Blocks  
Use the MULT18X18SIO primitive shown in Figure 34 to  
to the MULT18X18SIO multiplier ports and set the individual  
AREG, BREG, and PREG attributes to ‘1’ to insert the asso-  
ciated register, or to 0 to remove it and make the signal path  
combinatorial.  
instantiate a multiplier within a design. Although high-level  
logic synthesis software usually automatically infers a multi-  
plier, adding the pipeline registers usually requires the  
MULT18X18SIO primitive. Connect the appropriate signals  
DS312-2 (v1.1) March 21, 2005  
www.xilinx.com  
35  
Advance Product Specification