R
Functional Description
There are a number of different conditions under which data
can be accessed at the DO outputs. Basic data access
always occurs when the WE input is inactive. Under this
condition, data stored in the memory location addressed by
the ADDR lines passes through a output latch to the DO
outputs. The timing for basic data access is shown in the
portions of Figure 30, Figure 31, and Figure 32 during
which WE is Low.
Data also can be accessed on the DO outputs when assert-
ing the WE input based on the value of the WRITE_MODE
attribute as described in Table 23.
Table 23: WRITE_MODE Effect on Data Output Latches During Write Operations
Effect on Opposite Port
(dual-port only with same address)
Write Mode
Effect on Same Port
WRITE_FIRST
Read After Write
Data on DI and DIP inputs is written into
specified RAM location and simultaneously
appears on DO and DOP outputs.
Invalidates data on DO and DOP outputs.
READ_FIRST
Read Before Write
Data from specified RAM location appears on
DO and DOP outputs.
Data from specified RAM location appears on
DO and DOP outputs.
Data on DI and DIP inputs is written into
specified location.
NO_CHANGE
No Read on Write
Data on DO and DOP outputs remains
unchanged.
Invalidates data on DO and DOP outputs.
Data on DI and DIP inputs is written into
specified location.
Internal
Memory
DO
Data_in
CLK
Data_out = Data_in
DI
WE
DI
XXXX
aa
1111
bb
2222
cc
XXXX
ADDR
DO
dd
0000
MEM(aa)
1111
2222
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS312-2_05_020905
Figure 30: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Setting the WRITE_MODE attribute to a value of
Setting the WRITE_MODE attribute to a value of
READ_FIRST, data already stored in the addressed loca-
tion passes to the DO outputs before that location is over-
written with new data from the DI inputs on an enabled
active CLK edge. READ_FIRST timing is shown in the por-
tion of Figure 31 during which WE is High.
WRITE_FIRST, data is written to the addressed memory
location on an enabled active CLK edge and is also passed
to the DO outputs. WRITE_FIRST timing is shown in the
portion of Figure 30 during which WE is High.
DS312-2 (v1.1) March 21, 2005
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33
Advance Product Specification
XILINX [ XILINX, INC ]
