R
Functional Description
Table 21: Block RAM Attributes (Continued)
Function
Attribute
Possible Values
Data Output Latch Synchronous
Set/Reset Value
SRVAL(single-port)
SRVAL_A, SRVAL_B
(dual-port)
Hex value the width of the chosen port.
Data Output Latch Behavior during Write
WRITE_MODE
WRITE_FIRST, READ_FIRST, NO_CHANGE
(see Block RAM Data Operations)
The waveforms for the write operation are shown in the top
half of Figure 30, Figure 31, and Figure 32. When the WE
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports. Table 22 describes the data opera-
tions of each port as a result of the block RAM control sig-
nals in their default active-High edges.
Table 22: Block RAM Function Table
Input Signals
Output Signals
RAM Data
Parity
GSR EN SSR WE CLK ADDR
Immediately After Configuration
Loaded During Configuration
DIP
DI
DOP
DO
Data
X
X
INITP_xx
No Chg
No Chg
No Chg
INIT_xx
No Chg
No Chg
No Chg
Global Set/Reset Immediately After Configuration
1
0
0
0
X
0
1
1
X
X
1
1
X
X
0
1
X
X
↑
↑
X
X
X
X
X
INIT
RAM Disabled
No Chg
INIT
X
X
No Chg
Synchronous Set/Reset
SRVAL
X
X
SRVAL
Synchronous Set/Reset During Write RAM
addr
pdata Data
SRVAL
SRVAL
RAM(addr)
RAM(addr)
← pdata
← data
Read RAM, no Write Operation
RAM(pdata)
0
0
1
1
0
0
0
1
↑
↑
addr
X
X
RAM(data)
No Chg
No Chg
Write RAM, Simultaneous Read Operation
addr pdata Data WRITE_MODE = WRITE_FIRST
pdata
RAM(data)
No Chg
data
RAM(addr)
← pdata
RAM(addr)
← data
WRITE_MODE = READ_FIRST
RAM(data)
RAM(addr)
← pdata
RAM(addr)
← pdata
WRITE_MODE = NO_CHANGE
No Chg
RAM(addr)
RAM(addr)
← pdata
← pdata
32
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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