R
Functional Description
I
SRLC16
SHIFTIN
SRLC16E
D
CE
Q
Q15
CLK
SHIFT-REG
A0
A1
A2
A3
4
Output
D
A[3:0]
A[3:0]
MC15
Registered
Output
D
Q
DI
WS
DS312-2_43_021305
DI (BY)
(optional)
Figure 26: SRL16 Shift Register Component with
WSG
Cascade and Clock Enable
CE (SR)
CLK
WE
CK
The functionality of the shift register is shown in Table 17.
The SRL16 shifts on the rising edge of the clock input when
the Clock Enable control is High. This shift register cannot
be initialized either during configuration or during operation
except by shifting data into it. The clock enable and clock
inputs are shared between the two LUTs in a SLICEM. The
clock enable input is automatically kept active if unused.
SHIFTOUT
or YB
X465_03_040203
Figure 25: Logic Cell SRL16 Structure
Each shift register provides a shift output MC15 for the last
bit in each LUT, in addition to providing addressable access
to any bit in the shift register through the normal D output.
The address inputs A[3:0] are the same as the distributed
RAM address lines, which come from the LUT inputs F[4:1]
or G[4:1]. At the end of the shift register, the CLB flip-flop
can be used to provide one more shift delay for the addres-
sable bit.
Table 17: SRL16 Shift Register Function
Inputs
Outputs
Am
Am
Am
CLK
CE
0
D
X
D
Q
Q15
Q[15]
Q[15]
X
Q[Am]
↑
1
Q[Am-1]
The shift register element is known as the SRL16 (Shift
Register LUT 16-bit), with a ‘C’ added to signify a cascade
ability (Q15 output) and ‘E’ to indicate a Clock Enable. See
Figure 26 for an example of the SRLC16E component.
Notes:
1. m = 0, 1, 2, 3.
For more information on the SRL16, refer to XAPP465:
"Using Look-Up Tables as Shift Registers (SRL16) in
Spartan-3 FPGAs".
26
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
