R
Functional Description
Parity
Data
Address
35 34 33 32 31
P3 P2 P1 P0
24 23
16 15
8 7
0
Byte 3
Byte 2
Byte 1
Byte 0
512x36
0
17 16 15
P3 P2
8
7
0
Byte 3
Byte 1
Byte 2
Byte 0
1
0
1Kx18
P1 P0
8
7
0
P3
P2
P1
P0
Byte 3
Byte 2
Byte 1
Byte 0
3
2
1
0
2Kx9
3
2 1 0
7 6 5 4
3 2 1 0
7
6
4Kx4
7 6 5 4
3 2 1 0
1
0
1
0
7 6
5 4
3 2
1 0
F
E
D
C
8Kx2
7 6
5 4
3 2
1 0
3
2
1
0
0
7
6
5
4
1F
1E
1D
1C
16Kx1
3
2
1
0
3
2
1
0
DS312-2_02_020705
Figure 28: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B
defined in Table 20. The control signals (WE, EN, CLK, and
SSR) on the block RAM are active High. However, optional
inverters on the control signals change the polarity of the
active edge to active Low.
Block RAM Port Signal Definitions
Representations
of
the
dual-port
primitive
RAMB16_S[wA]_S[wB] and the single-port primitive
RAMB16_S[w] with their associated signals are shown in
Figure 29a and Figure 29b, respectively. These signals are
DS312-2 (v1.1) March 21, 2005
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29
Advance Product Specification
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