R
Functional Description
RAMB16_wA_wB
WEA
ENA
SSRA
DOPA[pA–1:0]
CLKA
DOA[wA–pA–1:0]
ADDRA[rA–1:0]
DIA[wA–pA–1:0]
DIPA[pA–1:0]
RAMB16_Sw
WEB
ENB
WE
EN
SSRB
SSR
DOPB[pB–1:0]
DOP[p–1:0]
CLKB
CLK
DOB[wB–pB–1:0]
DO[w–p–1:0]
ADDRB[rB–1:0]
DIB[wB–pB–1:0]
DIPB[pB–1:0]
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
(a) Dual-Port
(b) Single-Port
DS312-2_03_021305
Notes:
1.
2.
3.
w and w are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
A B
p
and p are integers that indicate the number of data path lines serving as parity bits.
A
B
r
and r are integers representing the address bus width at ports A and B, respectively.
B
A
4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Figure 29: Block RAM Primitives
Table 20: Block RAM Port Signals
Port A
Signal
Name
Port B
Signal
Name
Signal
Description
Direction
Function
Address Bus
ADDRA
ADDRB
Input
The Address Bus selects a memory location for read or write
operations. The width (w) of the port’s associated data path
determines the number of available address lines (r), as per
Table 18.
Data Input Bus
DIA
DIB
Input
Input
Data at the DI input bus is written to the RAM location specified
by the address input bus (ADDR) during the active edge of the
CLK input, when the clock enable (EN) and write enable (WE)
inputs are active.
It is possible to configure a port’s DI input bus width (w-p) based
on Table 18. This selection applies to both the DI and DO paths
of a given port.
Parity Data
Input(s)
DIPA
DIPB
Parity inputs represent additional bits included in the data input
path. Although referred to herein as “parity” bits, the parity inputs
and outputs have no special functionality for generating or
checking parity and can be used as additional data bits. The
number of parity bits ‘p’ included in the DI (same as for the DO
bus) depends on a port’s total data path width (w). See Table 18.
30
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
