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XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
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Functional Description  
Table 11: Carry Logic Functions (Continued)  
Function  
Description  
CYMUXG Carry generation or propagation mux for top half of slice. Dynamic selection via CYSELF of:  
CYMUXF carry propagation (CYSELG = 1)  
CY0G carry generation (CYSELG = 0)  
CYSELF  
CYSELG  
XORF  
Carry generation or propagation select for bottom half of slice. Fixed selection of:  
F-LUT output (typically XOR result)  
Fixed "1" to always propagate  
Carry generation or propagation select for top half of slice. Fixed selection of:  
G-LUT output (typically XOR result)  
Fixed "1" to always propagate  
Sum generation for bottom half of slice. Inputs from:  
F-LUT  
CYINIT carry signal from previous stage  
Result is sent to either the combinatorial or registered output for the top of the slice.  
XORG  
FAND  
GAND  
Sum generation for top half of slice. Inputs from:  
G-LUT  
CYMUXF carry signal from previous stage  
Result is sent to either the combinatorial or registered output for the top of the slice.  
Multiplier partial product for bottom half of slice. Inputs:  
F-LUT F1 input  
F-LUT F2 input  
Result is sent through CY0F to become the carry generate signal into CYMUXF  
Multiplier partial product for top half of slice. Inputs:  
G-LUT G1 input  
G-LUT G2 input  
Result is sent through CY0G to become the carry generate signal into CYMUXG  
The basic usage of the carry logic is to generate a half-sum  
in the LUT via an XOR function, which generates or propa-  
gates a carry out COUT via the carry mux CYMUXF (or  
CYMUXG), and then complete the sum with the dedicated  
XORF (or XORG) gate and the carry input CIN. This struc-  
ture allows two bits of an arithmetic function in each slice.  
The CYMUXF (or CYMUXG) can be instantiated using the  
MUXCY element, and the XORF (or XORG) can be instan-  
tiated using the XORCY element.  
The FAND (or GAND) gate is used for partial product multi-  
plication and can be instantiated using the MULT_AND  
component. Partial products are generated by two-input  
AND gates and then added. The carry logic is efficient for  
the adder, but one of the inputs must be outside the LUT as  
shown in Figure 20. The FAND (or GAND) gate is used to  
duplicate one of the partial products, while the LUT gener-  
ates both partial products and the XOR function, as shown  
in Figure 21.  
LUT  
COUT  
LUT  
B
COUT  
Am  
Bn+1  
MUXCY  
A
Am+1  
Bn  
Sum  
Pm+1  
XORCY  
CIN  
DS312-2_37_021305  
MULT_AND  
CIN  
DS312-2_39_021305  
Figure 20: Using the MUXCY and XORCY in the Carry  
Figure 21: Using the MULT_AND for Multiplication in  
Logic  
Carry Logic  
22  
www.xilinx.com  
DS312-2 (v1.1) March 21, 2005  
Advance Product Specification  
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