R
Functional Description
block RAM’s shared connectivity with the multipliers are
located in XAPP463.
Block RAM
Spartan-3E devices incorporate 4 to 36 dedicated block
RAMs, which are organized as dual-port configurable
18 Kbit blocks. Functionally, the block RAM is identical to
the Spartan-3 architecture block RAM. Block RAM synchro-
nously stores large amounts of data while distributed RAM,
previously described, is better suited for buffering small
amounts of data anywhere along signal paths. This section
describes basic block RAM functions. For detailed imple-
mentation information, refer to XAPP463: "Using Block
RAM in Spartan-3 Series FPGAs".
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical
data ports called A and B permit independent access to the
common block RAM, which has a maximum capacity of
18,432 bits, or 16,384 bits with no parity bits (see parity bits
description in Table 19). Each port has its own dedicated
set of data, control, and clock lines for synchronous read
and write operations. There are four basic data paths, as
shown in Figure 27:
Each block RAM is configurable by setting the content’s ini-
tial values, default signal value of the output registers, port
aspect ratios, and write modes. Block RAM can be used in
single-port or dual-port modes.
1. Write to and read from Port A
2. Write to and read from Port B
3. Data transfer from Port A to Port B
4. Data transfer from Port B to Port A
Arrangement of RAM Blocks on Die
The block RAMs are located together with the multipliers on
the die in one or two columns depending on the size of the
device. The XC3S100E has one column of block RAM. The
Spartan-3E devices ranging from the XC3S250E to
XC3S1600E have two columns of block RAM. Table 18
shows the number of RAM blocks, the data storage capac-
ity, and the number of columns for each device. Row(s) of
CLBs are located above and below each block RAM col-
umn.
3
Write
Read
Read
Write
4
Spartan-3E
Dual-Port
Block RAM
Write
Write
2
1
Read
Read
Table 18: Number of RAM Blocks by Device
DS312-2_01_020705
Total
Number of
RAM
Total
Addressable
Locations
(bits)
Figure 27: Block RAM Data Paths
Number
of
Columns
Number of Ports
Device
Blocks
A choice among primitives determines whether the block
RAM functions as dual- or single-port memory. A name of
the form RAMB16_S[wA]_S[wB] calls out the dual-port prim-
itive, where the integers wA and wB specify the total data
path width at ports A and B, respectively. Thus, a
RAMB16_S9_S18 is a dual-port RAM with a 9-bit Port A
and an 18-bit Port B. A name of the form RAMB16_S[w]
identifies the single-port primitive, where the integer w
specifies the total data path width of the lone port A. A
RAMB16_S18 is a single-port RAM with an 18-bit port.
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
4
73,728
221,184
368,640
516,096
663,552
1
2
2
2
2
12
20
28
36
Immediately adjacent to each block RAM is an embedded
18x18 hardware multiplier. The upper 16 bits of the block
RAM's Port A Data input bus are shared with the upper 16
bits of the A multiplicand input bus of the multiplier. Similarly,
the upper 16 bits of Port B's data input bus are shared with
the B multiplicand input bus of the multiplier. Details on the
Port Aspect Ratios
Each port of the block RAM can be configured indepen-
dently to select a number of different possible widths for the
data input (DI) and data output (DO) signals as shown in
Table 19.
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
27
Advance Product Specification
XILINX [ XILINX, INC ]
