欢迎访问ic37.com |
会员登录 免费注册
发布采购

XC2V1000-4FG456C 参数 Datasheet PDF下载

XC2V1000-4FG456C图片预览
型号: XC2V1000-4FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Virtex -II FPGA平台:完整的数据表 [Virtex-II Platform FPGAs: Complete Data Sheet]
分类和应用: 可编程逻辑时钟
文件页数/大小: 311 页 / 1765 K
品牌: XILINX [ XILINX, INC ]
 浏览型号XC2V1000-4FG456C的Datasheet PDF文件第5页浏览型号XC2V1000-4FG456C的Datasheet PDF文件第6页浏览型号XC2V1000-4FG456C的Datasheet PDF文件第7页浏览型号XC2V1000-4FG456C的Datasheet PDF文件第8页浏览型号XC2V1000-4FG456C的Datasheet PDF文件第10页浏览型号XC2V1000-4FG456C的Datasheet PDF文件第11页浏览型号XC2V1000-4FG456C的Datasheet PDF文件第12页浏览型号XC2V1000-4FG456C的Datasheet PDF文件第13页  
0
40  
R
Virtex™-II Platform FPGAs:  
Detailed Description  
0
0
DS031-2 (v3.0) August 1, 2003  
Product Specification  
Detailed Description  
Input/Output Blocks (IOBs)  
Table 1: Supported Single-Ended I/O Standards  
Virtex-II I/O blocks (IOBs) are provided in groups of two or  
four on the perimeter of each device. Each IOB can be used  
as input and/or output for single-ended I/Os. Two IOBs can  
be used as a differential pair. A differential pair is always  
connected to the same switch matrix, as shown in Figure 1.  
Board  
Termination  
I/O  
Standard  
Output  
VCCO  
Input  
VCCO  
Input  
VREF  
Voltage (VTT  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
1.2  
)
LVTTL  
3.3  
3.3  
2.5  
1.8  
1.5  
3.3  
3.3  
3.3  
3.3  
3.3  
2.5  
1.8  
1.5  
3.3  
3.3  
3.3  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
0.8  
LVCMOS33  
LVCMOS25  
LVCMOS18  
LVCMOS15  
PCI33_3  
PCI66_3  
PCI-X  
IOB blocks are designed for high performances I/Os, sup-  
porting 19 single-ended standards, as well as differential  
signaling with LVDS, LDT, Bus LVDS, and LVPECL.  
IOB  
PAD4  
Differential Pair  
IOB  
PAD3  
Switch  
GTL  
Note (1) Note (1)  
Note (1) Note (1)  
Matrix  
IOB  
GTLP  
1.0  
1.5  
PAD2  
Differential Pair  
HSTL_I  
1.5  
1.5  
1.5  
1.5  
1.8  
1.8  
1.8  
1.8  
2.5  
2.5  
3.3  
3.3  
3.3  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
0.75  
0.75  
0.9  
0.75  
0.75  
1.5  
IOB  
PAD1  
HSTL_II  
HSTL_III  
HSTL_IV  
HSTL_I  
DS031_30_101600  
Figure 1: Virtex-II Input/Output Tile  
0.9  
1.5  
0.9  
0.9  
Note: Differential I/Os must use the same clock.  
HSTL_II  
HSTL_III  
HSTL_IV  
SSTL2_I  
SSTL2_II  
SSTL3_I  
SSTL3_II  
AGP-2X/AGP  
Notes:  
0.9  
0.9  
Supported I/O Standards  
1.1  
1.8  
Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-  
puts that support a wide variety of I/O signaling standards.  
In addition to the internal supply voltage (VCCINT = 1.5V),  
output driver supply voltage (VCCO) is dependent on the  
I/O standard (see Table 1). An auxiliary supply voltage  
(VCCAUX = 3.3 V) is required, regardless of the I/O stan-  
dard used. For exact supply voltage absolute maximum rat-  
ings, see DC Input and Output Levels in Module 3.  
1.1  
1.8  
1.25  
1.25  
1.5  
1.25  
1.25  
1.5  
1.5  
1.5  
1.32  
N/A  
1. VCCO of GTL or GTLP should not be lower than the  
termination voltage or the voltage seen at the I/O pad.  
© 2001-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS031-2 (v3.0) August 1, 2003  
Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 2 of 4  
1
 复制成功!