R
Virtex™-II Platform FPGAs: Detailed Description
Table 2: Supported Differential Signal I/O Standards
Table 3: Supported DCI I/O Standards
Output
VCCO
Input
VCCO
Input
VREF
Output
VOD
I/O
Standard
Output Input
Input
VREF
Termination
Type
I/O Standard
LVPECL_33
LDT_25
VCCO
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
VCCO
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
LVDCI_33(1)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.8
Series
Series
Series
Series
Series
Series
Series
Series
Single
Single
Split
3.3
2.5
3.3
2.5
3.3
2.5
2.5
2.5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
490 mV to 1.22V
0.430 - 0.670
0.250 - 0.400
0.250 - 0.400
0.330 - 0.700
0.330 - 0.700
0.250 - 0.450
0.430 - 0.670
LVDCI_DV2_33(1)
LVDCI_25(1)
LVDS_33
LVDCI_DV2_25(1)
LVDCI_18(1)
LVDS_25
LVDSEXT_33
LVDSEXT_25
BLVDS_25
ULVDS_25
LVDCI_DV2_18(1)
LVDCI_15(1)
LVDCI_DV2_15(1)
GTL_DCI
GTLP_DCI
1.0
All of the user IOBs have fixed-clamp diodes to VCCO and
to ground. As outputs, these IOBs are not compatible or
compliant with 5V I/O standards. As inputs, these IOBs are
not normally 5V tolerant, but can be used with 5V I/O stan-
dards when external current-limiting resistors are used. For
more details, see the “5V Tolerant I/Os“ Tech Topic at
www.xilinx.com.
HSTL_I_DCI
0.75
0.75
0.9
HSTL_II_DCI
Split
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL2_I_DCI(2)
SSTL2_II_DCI(2)
SSTL3_I_DCI(2)
SSTL3_II_DCI(2)
Notes:
Single
Single
Split
0.9
0.9
0.9
Split
Table 3 lists supported I/O standards with Digitally Con-
trolled Impedance. See Digitally Controlled Impedance
(DCI), page 8.
1.08
1.08
1.25
1.25
1.5
Single
Single
Split
Split
Split
1.5
Split
1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled
impedance buffers, matching the reference resistors or half
of the reference resistors.
2. These are SSTL compatible.
Logic Resources
IOB blocks include six storage elements, as shown in
Figure 2.
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in Figure 3. There are two input, output,
and 3-state data signals, each being alternately clocked out.
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
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