R
Virtex™-II Platform FPGAs: Detailed Description
The optional weak-keeper circuit is connected to each user
I/O pad. When selected, the circuit monitors the voltage on
the pad and weakly drives the pin High or Low. If the pin is
connected to a multiple-source signal, the weak-keeper
holds the signal in its last state if all drivers are disabled.
Maintaining a valid logic level in this way eliminates bus
chatter. An enabled pull-up or pull-down overrides the
weak-keeper circuit.
LVTTL sinks and sources current up to 24 mA. The current
is programmable for LVTTL and LVCMOS SelectI/O-Ultra
standards (see Table 4). Drive-strength and slew-rate con-
trols for each output driver, minimize bus transients. For
LVDCI and LVDCI_DV2 standards, drive strength and
slew-rate controls are not available.
Table 4: LVTTL and LVCMOS Programmable Currents (Sink and Source)
SelectI/O-Ultra
LVTTL
Programmable Current (Worst-Case Guaranteed Minimum)
2 mA
2 mA
2 mA
2 mA
2 mA
4 mA
4 mA
4 mA
4 mA
4 mA
6 mA
6 mA
6 mA
6 mA
6 mA
8 mA
8 mA
8 mA
8 mA
8 mA
12 mA
12 mA
12 mA
12 mA
12 mA
16 mA
16 mA
16 mA
16 mA
16 mA
24 mA
24 mA
24 mA
n/a
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
n/a
Figure 6 shows the SSTL2, SSTL3, and HSTL configura-
tions. HSTL can sink current up to 48 mA. (HSTL IV)
All Virtex-II IOBs support IEEE 1149.1 compatible boundary
scan testing.
Input Path
V
CCO
The Virtex-II IOB input path routes input signals directly to
internal logic and / or through an optional input flip-flop or
latch, or through the DDR input registers. An optional delay
element at the D-input of the storage element eliminates
pad-to-pad hold time. The delay is matched to the internal
clock-distribution delay of the Virtex-II device, and when
used, assures that the pad-to-pad hold time is zero.
Clamp
Diode
OBUF
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
PAD
threshold voltage, V . The need to supply V
imposes
REF
REF
constraints on which standards can be used in the same
bank. See I/O banking description.
V
V
= 3.3V
CCAUX
= 1.5V
CCINT
Output Path
V
REF
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output and / or the
3-state signal can be routed to the buffer directly from the
internal logic or through an output / 3-state flip-flop or latch,
or through the DDR output / 3-state registers.
DS031_24_100900
Figure 6: SSTL or HSTL SelectI/O-Ultra Standards
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. Virtex-II
uses two memory cells to control the configuration of an I/O
as an input. This is to reduce the probability of an I/O con-
figured as an input from flipping to an output when sub-
jected to a single event upset (SEU) in space applications.
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. In most sig-
naling standards, the output High voltage depends on an
externally supplied V
voltage. The need to supply V
CCO
CCO
imposes constraints on which standards can be used in the
same bank. See I/O banking description.
Prior to configuration, all outputs not involved in configura-
tion are forced into their high-impedance state. The
pull-down resistors and the weak-keeper circuits are inac-
tive. The dedicated pin HSWAP_EN controls the pull-up
resistors prior to configuration. By default, HSWAP_EN is
set high, which disables the pull-up resistors on user I/O
pins. When HSWAP_EN is set low, the pull-up resistors are
activated on user I/O pins.
I/O Banking
Some of the I/O standards described above require V
CCO
and V
voltages. These voltages are externally supplied
REF
and connected to device pins that serve groups of IOB
blocks, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
DS031-2 (v3.0) August 1, 2003
Product Specification
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1-800-255-7778
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