R
Virtex™-II Platform FPGAs: Detailed Description
The DDR mechanism shown in Figure 3 can be used to mir-
ror a copy of the clock on the output. This is useful for prop-
agating a clock along the data that has an identical delay. It
is also useful for multiple clock generation, where there is a
unique clock driver for every clock load. Virtex-II devices
can produce many copies of a clock with very little skew.
IOB
Input
DDR mux
Reg
OCK1
Reg
ICK1
Each group of two registers has a clock enable signal (ICE
for the input registers, OCE for the output registers, and
TCE for the 3-state registers). The clock enable signals are
active High by default. If left unconnected, the clock enable
for that storage element defaults to the active state.
Reg
3-State
OCK2
Reg
ICK2
Each IOB block has common synchronous or asynchronous
set and reset (SR and REV signals).
DDR mux
Reg
OCK1
SR forces the storage element into the state specified by the
SRHIGH or SRLOW attribute. SRHIGH forces a logic “1”.
SRLOW forces a logic “0”. When SR is used, a second input
(REV) forces the storage element into the opposite state. The
reset condition predominates over the set condition. The ini-
tial state after configuration or global initialization state is
defined by a separate INIT0 and INIT1 attribute. By default,
the SRLOW attribute forces INIT0, and the SRHIGH attribute
forces INIT1.
PAD
Reg
Output
OCK2
DS031_29_100900
Figure 2: Virtex-II IOB Block
DCM
180° 0°
FDDR
FDDR
D1
Q1
D1
Q1
CLOCK
CLK1
CLK1
Q
Q
DDR MUX
DDR MUX
D2
D2
Q2
CLK2
Q2
CLK2
(50/50 duty cycle clock)
DS031_26_100900
Figure 3: Double Data Rate Registers
For each storage element, the SRHIGH, SRLOW, INIT0,
and INIT1 attributes are independent. Synchronous or
asynchronous set / reset is consistent in an IOB block.
•
•
•
•
•
•
•
No set or reset
Synchronous set
Synchronous reset
All the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed.
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Each register or latch (independent of all other registers or
latches) (see Figure 4) can be configured as follows:
Asynchronous set and reset (preset and clear)
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
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