R
Virtex™-II Platform FPGAs: Detailed Description
The synchronous reset overrides a set, and an asynchro-
nous clear overrides a preset.
(O/T) 1
Attribute
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
Q1
D1
CE
(O/T) CE
(O/T) CLK1
CK1
SR REV
SR
Shared
by all
registers
FF1
DDR MUX
FF2
(OQ or TQ)
REV
FF
LATCH
D2
Q2
CE
Attribute
INIT1
INIT0
SRHIGH
SRLOW
(O/T) CLK2
(O/T) 2
CK2
SR REV
Reset Type
SYNC
ASYNC
DS031_25_110300
Figure 4: Register / Latch Configuration in an IOB Block
Values of the optional pull-up and pull-down resistors are in
the range 10 - 60 KΩ, which is the specification for V
when operating at 3.3V (from 3.0 to 3.6V only). The clamp
diode is always present, even when power is not.
Input/Output Individual Options
CCO
Each device pad has optional pull-up and pull-down in all
SelectI/O-Ultra configurations. Each device pad has
optional weak-keeper in LVTTL, LVCMOS, and PCI
SelectI/O-Ultra configurations, as illustrated in Figure 5.
V
CCO
Clamp
Diode
OBUF
Weak
Keeper
V
CCO
Program Current
10-60KΩ
PAD
V
CCO
10-60KΩ
V
= 3.3V
= 1.5V
Program
Delay
CCAUX
V
CCINT
IBUF
DS031_23_011601
Figure 5: LVTTL, LVCMOS or PCI SelectI/O-Ultra Standards
DS031-2 (v3.0) August 1, 2003
www.xilinx.com
Module 2 of 4
Product Specification
1-800-255-7778
4
XILINX [ XILINX, INC ]
