R
Virtex™-II Platform FPGAs: Detailed Description
Eight I/O banks result from dividing each edge of the FPGA
into two banks, as shown in Figure 7 and Figure 8. Each
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
bank has multiple V
nected to the same voltage. This voltage is determined by
the output standards in use.
pins, all of which must be con-
CCO
All V
nected to the V
devices, some V
pins for the largest device anticipated must be con-
REF
voltage and not used for I/O. In smaller
REF
pins used in larger devices do not con-
CCO
nect within the package. These unconnected pins can be
left unconnected externally, or, if necessary, they can be
connected to V
to permit migration to a larger device.
CCO
Bank 0
Bank 1
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different
input, output, and bi-directional standards in the same bank:
1. Combining output standards only. Output standards
with the same output V
requirement can be
CCO
combined in the same bank.
Compatible example:
Bank 5
Bank 4
SSTL2_I and LVDS_25_DCI outputs
Incompatible example:
SSTL2_I (output VCCO = 2.5V) and
LVCMOS33 (output VCCO = 3.3V) outputs
ug002_c2_014_112900
Figure 7: Virtex-II I/O Banks: Top View for Wire-Bond
2. Combining input standards only. Input standards
Packages (CS, FG, & BG)
with the same input V
and input V
requirements
CCO
REF
can be combined in the same bank.
Compatible example:
Some input standards require a user-supplied threshold
voltage (V
), and certain user-I/O pins are automatically
REF
LVCMOS15 and HSTL_IV inputs
configured as V
inputs. Approximately one in six of the
REF
Incompatible example:
I/O pins in the bank assume this role.
LVCMOS15 (input VCCO = 1.5V) and
LVCMOS18 (input VCCO = 1.8V) inputs
Incompatible example:
HSTL_I_DCI_18 (VREF = 0.9V) and
HSTL_IV_DCI_18 (VREF = 1.1V) inputs
Bank 1
Bank 0
3. Combining input standards and output standards.
Input standards and output standards with the same
input V
and output V
requirement can be
CCO
CCO
combined in the same bank.
Compatible example:
LVDS_25 output and HSTL_I input
Incompatible example:
LVDS_25 output (output VCCO = 2.5V) and
HSTL_I_DCI_18 input (input VCCO = 1.8V)
Bank 4
Bank 5
4. Combining bi-directional standards with input or
output standards. When combining bi-directional I/O
with other standards, make sure the bi-directional
standard can meet rules 1 through 3 above.
ds031_66_112900
Figure 8: Virtex-II I/O Banks: Top View for Flip-Chip
Packages (FF & BF)
5. Additional rules for combining DCI I/O standards.
V
pins within a bank are interconnected internally, and
REF
consequently only one V
each bank. However, for correct operation, all V
voltage can be used within
a. No more than one Single Termination type (input or
output) is allowed in the same bank.
REF
pins in
REF
the bank must be connected to the external reference volt-
age source.
Incompatible example:
HSTL_IV_DCI input and HSTL_III_DCI input
b. No more than one Split Termination type (input or
output) is allowed in the same bank.
The V
and the V
pins for each bank appear in the
REF
CCO
device pinout tables. Within a given package, the number of
and V pins can vary depending on the size of
V
Incompatible example:
REF
CCO
HSTL_I_DCI input and HSTL_II_DCI input
device. In larger devices, more I/O pins convert to V
REF
pins. Since these are always a superset of the V
pins
REF
The implementation tools will enforce these design rules.
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
6
XILINX [ XILINX, INC ]
