R
Virtex™-II Platform FPGAs: Detailed Description
Digitally Controlled Impedance (DCI)
Controlled Impedance Drivers (Series
Termination)
DCI can be used to provide a buffer with a controlled output
impedance. It is desirable for this output impedance to
match the transmission line impedance (Z). Virtex-II input
buffers also support LVDCI and LVDCI_DV2 I/O standards.
Today’s chip output signals with fast edge rates require ter-
mination to prevent reflections and maintain signal integrity.
High pin count packages (especially ball grid arrays) can
not accommodate external termination resistors.
Virtex-II XCITE DCI provides controlled impedance drivers
and on-chip termination for single-ended and differential
I/Os. This eliminates the need for external resistors, and
improves signal integrity. The DCI feature can be used on
any IOB by selecting one of the DCI I/O standards.
IOB
Z
Z
When applied to inputs, DCI provides input parallel termina-
tion. When applied to outputs, DCI provides controlled
impedance drivers (series termination) or output parallel
termination.
Virtex-II DCI
V
= 3.3 V, 2.5 V, 1.8 V or 1.5 V
CCO
DS031_51_110600
Figure 10: Internal Series Termination
DCI operates independently on each I/O bank. When a DCI
I/O standard is used in a particular I/O bank, external refer-
ence resistors must be connected to two dual-function pins
on the bank. These resistors, voltage reference of N transis-
tor (VRN) and the voltage reference of P transistor (VRP)
are shown in Figure 9.
Table 6: SelectI/O-Ultra Controlled Impedance Buffers
V
DCI
DCI Half Impedance
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
CCO
3.3 V
2.5 V
1.8 V
1.5 V
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
1 Bank
DCI
DCI
Controlled Impedance Drivers (Parallel
Termination)
DCI also provides on-chip termination for SSTL3, SSTL2,
HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or
transmitters on bidirectional lines.
DCI
DCI
V
CCO
Table 7 lists the on-chip parallel terminations available in Vir-
tex-II devices. V
that there is a V
GTLP_DCI, due to the on-chip termination resistor.
must be set according to Table 3. Note
CCO
R
(1%)
(1%)
REF
requirement for GTL_DCI and
CCO
VRN
VRP
Table 7: SelectI/O-Ultra Buffers With On-Chip Parallel
Termination
R
REF
External
On-Chip
GND
I/O Standard
SSTL3 Class I
SSTL3 Class II
SSTL2 Class I
SSTL2 Class II
HSTL Class I
HSTL Class II
HSTL Class III
HSTL Class IV
GTL
Termination
Termination
DS031_50_101200
(1)
Figure 9: DCI in a Virtex-II Bank
SSTL3_I
SSTL3_II
SSTL2_I
SSTL2_II
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
GTL
SSTL3_I_DCI
SSTL3_II_DCI
(1)
When used with a terminated I/O standard, the value of
resistors are specified by the standard (typically 50 Ω).
When used with a controlled impedance driver, the resistors
set the output impedance of the driver within the specified
range (25 Ω to 100 Ω). For all series and parallel termina-
tions listed in Table 6 and Table 7, the reference resistors
must have the same value for any given bank. One percent
resistors are recommended.
(1)
SSTL2_I_DCI
(1)
SSTL2_II_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
GTL_DCI
The DCI system adjusts the I/O impedance to match the two
external reference resistors, or half of the reference resis-
tors, and compensates for impedance changes due to volt-
age and/or temperature fluctuations. The adjustment is
done by turning parallel transistors in the IOB on or off.
GTLP
GTLP
GTLP_DCI
Notes:
1. SSTL Compatible
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
8
XILINX [ XILINX, INC ]
