R
Spartan-IIE FPGA Family: Pinout Tables
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
I/O (D5),
Bank Pin
Function
Bank Pin
3
L13
All
-
I/O, VREF
2
F16
XC2S50E,
All
-
L35N_YY
Bank 2, L28P
300E, 400E
I/O, L35P_YY
I/O, L34N
3
3
K14
All
-
-
I/O, L27N
2
H13
XC2S50E,
100E, 150E,
200E,
K15 XC2S100E,
150E, 400E
300E(1)
I/O, L34P
I/O, L33N
3
3
K16 XC2S100E,
150E, 400E
-
-
I/O, L27P
2
G14 XC2S50E,
100E, 150E,
200E,
-
L12
K12
XC2S50E,
100E,150E,
200E,
300E(2)
I/O, L26N
2
2
F15 XC2S100E,
150E, 400E
-
-
300E(1)
I/O, L33P
3
XC2S50E,
100E,150E,
200E,
-
I/O, L26P
E16 XC2S100E,
150E, 400E
300E(1)
I/O, L25N_YY
2
2
G13
F14
All
All
-
-
I/O, VREF
Bank 3, L32N
3
3
3
K13
J14
XC2S50E,
300E, 400E
All
-
I/O (D2),
L25P_YY
I/O (D4), L32P
I/O, L31N
XC2S50E,
I/O (D1), L24N
I/O, L24P
2
2
E15
D16
XC2S50E,
300E, 400E
-
300E, 400E
J15 XC2S100E,
150E,200E,
400E
-
XC2S50E, XC2S100E,
300E, 400E 150E,200E,
300E, 400E
I/O, L31P
3
J16 XC2S100E, XC2S400E
I/O, L23N
I/O, L23P
I/O, L22N
2
2
2
F13 XC2S150E,
200E, 400E
-
-
-
150E,200E,
400E
E14 XC2S150E,
200E, 400E
I/O (TRDY)
3
2
J13
-
-
D15
XC2S50E,
150E, 200E,
300E, 400E
I/O (IRDY),
L30N_YY
H16
G16
All
All
-
-
I/O, VREF
Bank 2, L22P
2
2
2
2
C16
XC2S50E,
150E, 200E,
300E, 400E
All
-
I/O, L30P_YY
I/O, L29N
2
2
H14 XC2S100E, XC2S400E
150E,200E,
400E
I/O, L21N
I/O, L21P
I/O, L20N
G12 XC2S50E,
100E, 200E,
300E
I/O, L29P
2
2
H15 XC2S100E,
150E,200E,
400E
-
-
F12
XC2S50E,
100E, 200E,
300E
-
I/O (D3), L28N
G15
XC2S50E,
300E, 400E
E13 XC2S100E,
200E, 300E
-
DS077-4 (2.3) June 18, 2008
www.xilinx.com
69
Product Specification
XILINX [ XILINX, INC ]
