R
Spartan-IIE FPGA Family: Pinout Tables
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
FT256 Differential Clock Pins
P
N
Pad Name
LVDS
Async.
Output
Option
Clock Bank
Pin
Name
Pin
Name
GCK0
GCK1
GCK2
GCK3
4
5
1
0
T9
GCK0, I
GCK1, I
GCK2, I
GCK3, I
R9
I/O (DLL),
L52P
VREF
Option
Function
I/O, L6P
Bank Pin
T8
B8
C8
R8
A8
D8
I/O (DLL),
L52N
0
C7
XC2S50E,
200E,300E,
400E
-
I/O (DLL),
L8P
I/O, L6N
0
B7
XC2S50E,
200E,300E,
400E
-
I/O (DLL),
L8N
I/O
0
0
A6
B6
-
-
-
I/O, L5P
XC2S50E,
100E,200E,
300E, 400E
Additional FT256 Package Pins
VCCINT Pins
I/O, L5N
I/O, L4P
I/O, L4N
0
0
0
C6
A5
B5
XC2S50E,
100E,200E,
300E, 400E
-
-
C3
C14
M5
D4
M12
-
D13
N4
-
E5
N13
-
E12
P3
P14
XC2S50E,
100E,200E,
300E, 400E
VCCO Bank 0 Pins
E8
F7
F8
-
-
-
-
-
-
-
-
-
-
XC2S50E, XC2S100E,
100E,200E, 150E,200E,
300E, 400E 300E, 400E
VCCO Bank 1 Pins
E9
F9
F10
H12
K11
M9
I/O, L3P
0
0
D6
E6
XC2S50E,
100E, 300E
-
VCCO Bank 2 Pins
G11
H11
I/O, L3N
XC2S50E,
100E, 300E
-
VCCO Bank 3 Pins
J11
J12
I/O, L2P_YY
0
0
D5
C5
All
All
-
VCCO Bank 4 Pins
I/O, VREF
Bank 0,
All
L9
L10
L2N_YY
I/O, L1P_YY
I/O, L1N_YY
I/O, L0P_YY
I/O, L0N_YY
0
0
0
0
B4
C4
A4
A3
All
All
All
All
-
-
-
XC2S200E,
300E, 400E
I/O
0
-
B3
A2
-
-
-
-
TCK
Notes:
1. Although designated with the _YY suffix in the XC2S50E,
XC2S100E, XC2S150E, XC2S200E, and XC2S300E, these
differential pairs are not asynchronous in the XC2S400E.
2. There is no pair L37.
DS077-4 (2.3) June 18, 2008
www.xilinx.com
71
Product Specification
XILINX [ XILINX, INC ]
