R
Spartan-IIE FPGA Family: Pinout Tables
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
I/O, L65P
Bank Pin
Function
I/O, L57P
Bank Pin
6
L4
XC2S50E,
150E,200E,
300E, 400E
-
5
5
5
5
5
P6
R6
T6
XC2S50E,
100E, 150E,
300E
-
I/O, VREF
Bank 6, L65N
6
L5
XC2S50E,
150E,200E,
300E, 400E
All
I/O, L56N
I/O, L56P
I/O, L55N
I/O, L55P
XC2S50E, XC2S100E,
100E, 200E, 150E,200E,
300E, 400E 300E, 400E
I/O, L64P_YY
I/O, L64N_YY
I/O, L63P
6
6
6
M3
M4
N2
All
All
-
-
-
XC2S50E,
100E, 200E,
300E, 400E
-
-
-
XC2S100E,
200E, 300E
M6
N7
XC2S50E,
100E, 200E,
300E, 400E
I/O, L63N
6
N3
XC2S100E, XC2S200E,
200E, 300E 300E, 400E
XC2S50E,
100E, 200E,
300E, 400E
I/O, L62P_YY
6
6
-
P1
P2
R1
T2
R3
All
All
-
-
-
-
-
-
I/O, L62N_YY
I/O
5
5
P7
R7
-
-
-
M1
M0
M2
I/O, L54N
XC2S50E,
200E, 300E,
400E
-
-
-
-
I/O, L54P
5
5
5
T7
M7
N8
XC2S50E,
200E, 300E,
400E
-
All
-
I/O, L61N_YY
I/O, L61P_YY
I/O, L60N
5
5
5
P4
R4
T3
All
All
-
-
I/O, VREF
Bank 5, L53N
XC2S50E,
200E, 300E,
400E
XC2S50E, XC2S200E,
100E,200E, 300E, 400E
300E, 400E
I/O, L53P
XC2S50E,
200E, 300E,
400E
I/O, L60P
5
T4
XC2S50E,
100E,200E,
300E, 400E
-
I/O
5
5
P8
R8
-
-
XC2S400E
-
I/O, L59N_YY
I/O, L59P_YY
5
5
5
N5
P5
R5
All
All
All
-
-
I/O (DLL),
L52N
I/O, VREF
Bank 5,
All
GCK1, I
5
T8
-
-
L58N_YY
GCK0, I
4
4
T9
-
-
-
-
I/O, L58P_YY
I/O, L57N
5
5
T5
N6
All
-
-
I/O (DLL),
L52P
R9
XC2S50E,
100E,150E,
300E
I/O, L51N
4
P9
XC2S50E, XC2S400E
150E, 200E,
400E
DS077-4 (2.3) June 18, 2008
www.xilinx.com
67
Product Specification
XILINX [ XILINX, INC ]
