R
Spartan-IIE FPGA Family: Pinout Tables
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E,
XC2S400E)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
Function
I/O, L74P
Bank Pin
VREF
Option
Function
TMS
I/O
Bank Pin
7
H4
XC2S100E,
150E, 200E
-
-
B1
D3
C2
-
-
-
-
-
I/O, L74N
7
H3
XC2S100E, XC2S400E
150E, 200E
7
7
I/O, L83P
XC2S100E,
150E
I/O, L73P_YY
7
7
H2
H1
All
All
-
-
I/O (IRDY),
L73N_YY
I/O, L83N
7
C1
XC2S100E, XC2S200E,
150E
300E, 400E
I/O, L82P_YY
I/O, L82N_YY
7
7
7
D2
D1
E3
All
-
-
I/O (TRDY)
I/O, L72P
6
6
J4
J2
-
-
All
XC2S100E, XC2S400E
150E, 200E,
I/O, VREF
Bank 7, L81P
XC2S50E,
150E,200E,
300E, 400E
All
400E
I/O, L72N
I/O, L71P
6
J3
XC2S100E,
150E, 200E,
400E
-
I/O, L81N
7
E4
XC2S50E,
150E,200E,
300E, 400E
-
6
6
J1
XC2S50E,
300E, 400E
-
I/O, L80P
I/O, L80N
I/O, L79P
7
7
7
E2
E1
F4
XC2S200E,
400E
-
-
I/O, VREF
Bank 6, L71N
K1
XC2S50E,
300E, 400E
All
XC2S200E,
400E
I/O, L70P_YY
I/O, L70N_YY
I/O, L69P
6
6
6
K2
K3
L1
All
All
-
-
-
XC2S50E, XC2S100E,
300E, 400E 150E,200E,
300E, 400E
XC2S100E,
150E, 400E
I/O, L79N
7
F3
XC2S50E,
300E, 400E
-
I/O, L69N
6
L2
XC2S100E,
150E, 400E
-
I/O, L78P_YY
I/O, L78N_YY
I/O, L77P
7
7
7
F2
F1
F5
All
All
-
-
-
I/O, L68P_YY
I/O, L68N_YY
I/O, L67P
6
6
6
K4
K5
L3
All
All
-
-
-
XC2S100E,
150E
XC2S50E,
300E, 400E
I/O, L77N
7
G5 XC2S100E,
150E
-
I/O, L67N
6
M2
XC2S50E, XC2S100E,
300E, 400E 150E,200E,
300E, 400E
I/O, L76P_YY
I/O, L76N_YY
7
7
7
G3
G4
G2
All
All
-
-
I/O, L66P
I/O, L66N
6
6
M1 XC2S150E,
200E, 400E
-
I/O, VREF
Bank 7, L75P
XC2S50E,
300E, 400E
All
N1
XC2S150E,
200E, 400E
-
I/O, L75N
7
G1
XC2S50E,
300E, 400E
-
66
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DS077-4 (2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
