R
Spartan-IIE FPGA Family: Pinout Tables
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
Bank
Pin
Function
I/O
Bank
Pin
I/O, VREF
Bank 1, L6P
1
P178 XC2S50E,
200E, 300E
All
-
0
0
P201
P202
-
-
-
I/O,
All
I/O, L6N
1
P179 XC2S50E,
200E, 300E
L0P_YY
I/O, VREF
Bank 0,
L0N_YY
0
P203
All
All
I/O
1
1
P180
P181
-
-
-
-
I/O (DLL),
L5P
I/O
I/O
0
0
P204
P205
-
-
-
GCK2, I
GND
1
-
P182
P183
P184
-
-
-
-
-
-
XC2S200E,
300E
I/O
0
-
P206
P207
P208
-
-
-
-
-
-
VCCO
-
TCK
VCCO
-
GCK3, I
VCCINT
0
-
P185
P186
P187
-
-
-
-
-
-
PQ208 Differential Clock Pins
I/O (DLL),
L5N
0
P
N
Clock Bank
Pin
Name
Pin
Name
I/O, L4P
0
0
P188 XC2S50E,
200E, 300E
-
GCK0
GCK1
GCK2
GCK3
4
5
1
0
P80 GCK0, I
P81
I/O (DLL),
L31P
I/O, VREF
Bank 0, L4N
P189 XC2S50E,
200E, 300E
All
P77 GCK1, I
P75
I/O (DLL),
L31N
GND
-
P190
-
-
-
P182 GCK2, I P181
P185 GCK3, I P187
I/O (DLL),
L5P
I/O, L3P
0
P191 XC2S50E,
200E, 300E
I/O (DLL),
L5N
I/O, L3N
I/O, L2P
0
0
P192 XC2S50E,
200E, 300E
-
-
P193 XC2S50E,
100E, 200E,
300E
I/O, L2N
0
P194 XC2S50E,
100E, 200E,
300E
-
VCCINT
VCCO
GND
-
-
P195
P196
P197
-
-
-
-
-
-
-
-
I/O, L1P
0
P198 XC2S50E,
100E, 200E,
300E
I/O, L1N
I/O
0
0
P199 XC2S50E, XC2S100E,
100E, 200E, 150E, 200E,
300E
300E
P200
-
-
DS077-4 (2.3) June 18, 2008
www.xilinx.com
65
Product Specification
XILINX [ XILINX, INC ]
