R
Spartan-IIE FPGA Family: Pinout Tables
Pinout Tables
The following device-specific pinout tables include all pack-
ages available for each Spartan-IIE device. They follow the
pad locations around the die. In the TQ144 package, all
VCCO pins must be connected to the same voltage.
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
LVDS
Async.
Output
Option
VREF
Option
TQ144 Pinouts (XC2S50E and XC2S100E)
Function
I/O, L22N
Bank
Pin
6
6
6
P27 XC2S50E XC2S100E
Pad Name
LVDS
Async.
Output
Option
I/O
P28
P29
-
-
-
VREF
Option
I/O, VREF
Bank 6
All
Function
GND
Bank
Pin
P1
P2
P3
P4
P5
-
-
-
-
-
-
-
-
-
I/O
6
6
6
-
P30
P31
P32
P33
P34
P35
P36
P37
-
All
All
-
-
-
-
-
-
-
-
-
TMS
I/O
I/O, L21P_YY
I/O, L21N_YY
M1
7
7
7
-
I/O
-
I/O, VREF
Bank 7
All
GND
-
-
M0
-
-
I/O
7
7
7
-
P6
P7
-
-
VCCO
M2
-
-
I/O, L27P
I/O, L27N
GND
XC2S50E XC2S100E
-
-
P8
XC2S50E
-
-
P9
-
I/O, L20N_YY
I/O, L20P_YY
I/O
5
5
5
5
P38
P39
P40
P41
All
All
-
-
-
I/O, L26P_YY
I/O, L26N_YY
7
7
7
P10
P11
All
All
-
-
-
I/O, VREF
Bank 7, L25P
P12 XC2S50E
All
I/O, VREF
Bank 5
-
All
I/O, L25N
I/O
7
7
7
-
P13 XC2S50E
-
-
-
-
-
I/O
5
5
5
-
P42
P43
P44
P45
P46
P47
P48
P49
-
All
All
-
-
P14
P15
P16
P17
-
-
-
-
I/O, L19N_YY
I/O, L19P_YY
GND
XC2S100E
I/O (IRDY)
GND
-
-
VCCO
-
VCCINT
-
-
-
I/O, L18N_YY
I/O, L18P_YY
5
5
5
All
All
-
-
I/O (TRDY)
VCCINT
I/O
6
-
P18
P19
P20
-
-
-
-
-
-
I/O, VREF
Bank 5
All
6
6
6
-
I/O, L24P
P21 XC2S50E
P22 XC2S50E
-
I/O (DLL), L17N
VCCINT
GCK1, I
VCCO
5
-
P50
P51
P52
P53
P54
-
-
-
-
-
-
-
-
-
-
I/O, VREF
Bank 6, L24N
All
5
5
-
I/O, L23P_YY
I/O, L23N_YY
GND
6
6
-
P23
P24
P25
All
All
-
-
-
-
-
GND
I/O, L22P
6
P26 XC2S50E
GCK0, I
4
P55
-
-
58
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DS077-4 (2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
