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XC2S400E-6FG456C 参数 Datasheet PDF下载

XC2S400E-6FG456C图片预览
型号: XC2S400E-6FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- IIE FPGA [Spartan-IIE FPGA]
分类和应用:
文件页数/大小: 108 页 / 5063 K
品牌: XILINX [ XILINX, INC ]
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Spartan-IIE FPGA Family: Pinout Tables  
Pin Definitions (Continued)  
Dedicated  
Pad Name  
Pin  
Direction  
Description  
D0/DIN, D1, D2, D3,  
D4, D5, D6, D7  
No  
Input or Output In Slave Parallel mode, D0-D7 are configuration data input pins.  
During readback, D0-D7 are output pins. These pins become  
user I/Os after configuration unless the Slave Parallel port is  
retained.  
In serial modes, DIN is the single data input. This pin becomes a  
user I/O after configuration.  
WRITE  
CS  
No  
No  
Input  
Input  
In Slave Parallel mode, the active-low Write Enable signal. This  
pin becomes a user I/O after configuration unless the Slave  
Parallel port is retained.  
In Slave Parallel mode, the active-low Chip Select signal. This pin  
becomes a user I/O after configuration unless the Slave Parallel  
port is retained.  
TDI, TDO, TMS, TCK  
VCCINT  
Yes  
Yes  
Yes  
Mixed  
Input  
Input  
Boundary Scan Test Access Port pins (IEEE 1149.1).  
1.8V power supply pins for the internal core logic.  
VCCO  
Power supply pins for output drivers (1.5V, 1.8V, 2.5V, or 3.3V  
subject to banking rules in the Functional Description module.  
VREF  
No  
Input  
Input threshold reference voltage pins. Become user I/Os when  
an external threshold voltage is not needed (subject to banking  
rules in the Functional Description module.  
GND  
Yes  
No  
Input  
Ground. All must be connected.  
IRDY, TRDY  
See PCI core  
These signals can only be accessed when using Xilinx PCI cores.  
documentation If the cores are not used, these pins are available as user I/Os.  
L#[P/N]  
(e.g., L0P)  
No  
Bidirectional  
Differential I/O with synchronous output. P = positive, N =  
negative. The number (#) is used to associate the two pins of a  
differential pair. Becomes a general user I/O when not needed for  
differential signals.  
L#[P/N]_Y  
(e.g., L0P_Y)  
No  
Bidirectional  
Differential I/O with asynchronous or synchronous output  
(asynchronous output not compatible for all densities in a  
package). P = positive, N = negative. The number (#) is used to  
associate the two pins of a differential pair. Becomes a general  
user I/O when not needed for differential signals.  
L#[P/N]_YY  
(e.g., L0P_YY)  
No  
No  
Bidirectional  
Bidirectional  
Differential I/O with asynchronous or synchronous output  
(compatible for all densities in a package). P = positive, N =  
negative. The number (#) is used to associate the two pins of a  
differential pair. Becomes a general user I/O when not needed for  
differential signals.  
I/O  
These pins can be configured to be input and/or output after  
configuration is completed. Unused I/Os are disabled with a weak  
pull-down resistor. After power-on and before configuration is  
completed, these pins are either pulled up or left floating  
according to the Mode pin values. See the DC and Switching  
Characteristics module for power-on characteristics.  
54  
www.xilinx.com  
DS077-4 (2.3) June 18, 2008  
Product Specification  
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