R
Spartan-IIE FPGA Family: Pinout Tables
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
LVDS
Async.
Output
Option
Pad Name
LVDS
Async.
Output
Option
VREF
Option
VREF
Option
Function
Bank
Pin
Function
Bank
Pin
I/O
0
0
P139
P140
-
-
-
I/O (CS),
L5P_YY
1
1
P112
P113
All
All
-
-
I/O, VREF
Bank 0
All
I/O (WRITE),
L5N_YY
I/O
0
0
-
P141
P142
P143
P144
-
-
-
-
-
-
-
-
I/O
I/O
1
1
P114
P115
-
-
-
TCK
VCCO
I/O, VREF
Bank 1
All
-
I/O
1
1
1
-
P116
P117
P118
P119
P120
P121
P122
P123
-
All
All
-
-
TQ144 Differential Clock Pins
I/O, L4P_YY
I/O, L4N_YY
GND
XC2S100E
P
N
-
-
Clock Bank
Pin
Name
Pin
Name
GCK0
GCK1
GCK2
GCK3
4
5
1
0
P55 GCK0, I
P56
I/O (DLL),
L17P
VCCINT
-
-
-
I/O, L3P_YY
I/O, L3N_YY
1
1
1
All
All
-
-
P52 GCK1, I
P50
I/O (DLL),
L17N
-
P126 GCK2, I P125
P129 GCK3, I P131
I/O (DLL),
L2P
I/O, VREF
Bank 1
All
I/O (DLL),
L2N
I/O
1
1
1
-
P124
P125
P126
P127
P128
-
-
-
-
-
-
-
-
-
-
I/O (DLL), L2P
GCK2, I
GND
VCCO
-
GCK3, I
0
-
P129
P130
P131
P132
-
-
-
-
-
-
VCCINT
I/O (DLL), L2N
0
0
-
I/O, VREF
Bank 0
All
I/O, L1P_YY
I/O, L1N_YY
VCCINT
0
0
-
P133
P134
P135
P136
P137
P138
All
All
-
-
-
-
GND
-
-
-
I/O, L0P_YY
I/O, L0N_YY
0
0
All
All
-
XC2S100E
60
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DS077-4 (2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
