R
XC18V00 Series of In-System Programmable Configuration PROMs
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tol-
erant even through the core power supply is 3.3V. This
allows 5V CMOS signals to connect directly to the PROM
inputs without damage. In addition, the 3.3V VCC power
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (VCC), and the output power supply
(VCCO) can have power applied in any order. This makes
the PROM devices immune to power supply sequencing
issues.
low until the XC18V00 voltage reaches the operating volt-
age range. If the power drops below 2.0V, the PROM resets.
OE/RESET polarity is NOT programmable.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input. JTAG pins
TMS, TDI and TDO can be in a high-impedance state or
High.
Reset Activation
Customer Control Pins
On power up, OE/RESET is held low until the XC18V00 is
active (1 ms) and able to supply data after receiving a CCLK
pulse from the FPGA. OE/RESET is connected to an exter-
nal resistor to pull OE/RESET HIGH releasing the FPGA
INIT and allowing configuration to begin. OE/RESET is held
The XC18V00 PROMs have various control bits accessible
by the customer. These can be set after the array has been
programmed using “Skip User Array” in Xilinx JTAG Pro-
grammer Software.
Table 7: Truth Table for PROM Control Inputs
Control Inputs
Outputs
OE/RESET
CE
Internal Address
DATA
CEO
ICC
High
Low
If address < TC(1): increment
If address > TC(1): don’t change
Active
High-Z
High
Low
Active
Reduced
Low
High
Low
Low
High
High
Held reset
Held reset
Held reset
High-Z
High-Z
High-Z
High
High
High
Active
Standby
Standby
Notes:
1. TC = Terminal Count = highest address value. TC + 1 = address 0.
DS026 (v3.0) November 12, 2001
Product Specification
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11
XILINX [ XILINX, INC ]
