R
1/4th of Bourns
Part Number
CAT16-LV4F12
1/4th of Bourns
Part Number
CAT16-PT4F4
VCCO = 2.5V
VCCO = 2.5V
Z
0
0
= 50Ω
= 50Ω
165Ω
140Ω
100Ω
Z
165Ω
DS635_05_082807
Figure 5: External Termination Resistors for BLVDS Transmitter and BLVDS Receiver
Switching Characteristics
I/O Timing
Table 13: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
-4 Speed
Grade
Symbol
Description
Conditions
Device
Max
Units
Clock-to-Output Times
(2)
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
T
When reading from the Output
Flip-Flop (OFF), the time from
the active transition on the
Global Clock pin to data
appearing at the Output pin. The
DCM is used.
LVCMOS25 , 12mA
2.79
3.45
3.46
3.46
3.45
5.92
5.43
5.51
5.94
6.05
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ICKOFDCM
output drive, Fast slew rate,
(3)
with DCM
(2)
T
When reading from OFF, the
LVCMOS25 , 12mA
ICKOF
time from the active transition on output drive, Fast slew rate,
the Global Clock pin to data
appearing at the Output pin. The
DCM is not used.
without DCM
Notes:
1. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in
Table 6 and Table 9.
2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 17. If the latter is true, add the appropriate Output adjustment from Table 18.
3. DCM output jitter is included in all measurements.
4. For minimums, use the values reported by the Xilinx timing analyzer.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
14
XILINX [ XILINX, INC ]
